Datasheet

PIC18F66K80 FAMILY
DS39977C-page 194 Preliminary  2011 Microchip Technology Inc.
TABLE 11-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE
RE5/CANTX RE5
(1)
0 O DIG LATE<5> data output.
1 I ST PORTE<5> data input.
CANTX
(1,2)
0 O DIG CAN bus TX.
RE6/RX2/DT2 RE6
(1)
0 O DIG LATE<6> data output.
1 I ST PORTE<6> data input.
RX2
(1)
1 I ST Asynchronous serial receive data input (EUSART module).
DT2
(1)
1 O DIG Synchronous serial data output (EUSART module); takes priority over
port data.
1 I ST Synchronous serial data input (EUSART module); user must configure
as an input.
RE7/TX2/CK2 RE7
(1)
0 O DIG LATE<7> data output.
1 I ST PORTE<7> data input.
TX2
(1)
0 O DIG Asynchronous serial data output (EUSART module); takes priority over
port data.
CK2
(1)
0 O DIG Synchronous serial clock output (EUSART module); user must
configure as an input.
1 I ST Synchronous serial clock input (EUSART module); user must configure
as an input.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTE RE7
(1)
RE6
(1)
RE5
(1)
RE4
(1)
RE3 RE2 RE1 RE0
LATE LATE7 LATE6 LATE5 LATE4
— LATE2 LATE1 LATE0
TRISE TRISE7 TRISE6 TRISE5 TRISE4
— TRISE2 TRISE1 TRISE0
PADCFG1
RDPU REPU RFPU
(1)
RGPU
(1)
— — — CTMUDS
ANCON0 ANSEL7 ANSEL6 ANSEL5
ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0
Legend: Shaded cells are not used by PORTE.
Note 1: Unimplemented on 44-pin devices, read as ‘0’.
TABLE 11-9: PORTE FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O I/O Type Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Unavailable for 40 and 44-pin devices (PIC18F4XK0).
2: Alternate pin assignment for CANRX and CANTX on 64-pin devices (PIC18F6XK80) when the CANMX Configuration
bit is cleared.