Datasheet

PIC18F66K80 FAMILY
DS39977C-page 186 Preliminary  2011 Microchip Technology Inc.
TABLE 11-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB
RB5/T0CKI/T3CKI/
CCP5/KBI1
RB5 0 O DIG LATB<5> data output.
1 I ST PORTB<5> data input; weak pull-up when RBPU bit is cleared.
T0CKI
(3)
x I ST Timer0 clock input.
T3CKI
(4)
x I ST Timer3 clock input.
CCP5 0 O DIG CCP5 compare/PWM output. Takes priority over port data.
1 I ST CCP5 capture input.
KBI1 1 I ST Interrupt-on-pin change.
RB6/PGC/TX2/CK2/
KBI2
RB6 0 O DIG LATB<6> data output.
1 I ST PORTB<6> data input; weak pull-up when RBPU bit is cleared.
PGC x I ST Serial execution (ICSP™) clock input for ICSP and ICD operation.
TX2
(1)
0 O DIG Asynchronous serial data output (EUSART module); takes priority
over port data.
CK2
(1)
0 O DIG Synchronous serial clock output (EUSART module); user must
configure as an input.
1 I ST Synchronous serial clock input (EUSART module); user must
configure as an input.
KBI2 1 I ST Interrupt-on-pin change.
RB7/PGD/T3G/RX2/
DT2/KBI3
RB7 0 O DIG LATB<7> data output.
1 I ST PORTB<7> data input; weak pull-up when RBPU bit is cleared.
PGD x O DIG Serial execution data output for ICSP and ICD operation.
x I ST Serial execution data input for ICSP and ICD operation.
T3G x I ST Timer3 external clock gate input.
RX2
(1)
1 I ST Asynchronous serial receive data input (EUSART module).
DT2
(1)
1 O DIG Synchronous serial data output (AUSART module); takes priority
over port data.
1 I ST Synchronous serial data input (AUSART module); user must
configure as an input.
KBI3 1 I ST Interrupt-on-pin change.
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
INTCON
GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
INTCON2 RBPU
INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INT3IP RBIP
INTCON3 INT2IP INT1IP INT3IE INT2IE INT1IE INT3IF INT2IF INT1IF
ODCON
SSPOD CCP5OD CCP4OD CCP3OD CCP2OD CCP1OD U2OD U1OD
ANCON1
— ANSEL14 ANSEL13 ANSEL12 ANSEL11 ANSEL10 ANSEL9 ANSEL8
Legend: Shaded cells are not used by PORTB.
TABLE 11-3: PORTB FUNCTIONS (CONTINUED)
Pin Name Function
TRIS
Setting
I/O I/O Type Description
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pin assignment only available for 28-pin devices (PIC18F2XK80).
2: Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
3: Default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
4: Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices
when T3CKMX is cleared.