Datasheet

 2011 Microchip Technology Inc. Preliminary DS39977C-page 185
PIC18F66K80 FAMILY
TABLE 11-3: PORTB FUNCTIONS
Pin Name Function
TRIS
Setting
I/O I/O Type Description
RB0/AN10/C1INA
FLT0/INT0
RB0 0 O DIG LATB<0> data output.
1 I ST PORTB<0> data input; weak pull-up when RBPU bit is cleared.
AN10 1 I ANA A/D Input Channel 10 and Comparator C1+ input. Default input
configuration on POR.
C1INA
(1)
1 I ANA Comparator 1 Input A.
FLT0 x I ST Enhanced PWM Fault input for ECCPx.
INT0 1 I ST External Interrupt 0 input.
RB1/AN8/C1INB/
P1B/CTDIN/INT1
RB1 0 O DIG LATB<1> data output.
1 I ST PORTB<1> data input; weak pull-up when RBPU bit is cleared.
AN8 1 I ANA A/D Input Channel 8 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
C1INB
(1)
1 I ANA Comparator 1 Input B.
P1B
(1)
0 O DIG ECCP1 PWM Output B. May be configured for tri-state during
Enhanced PWM shutdown events.
CTDIN 1 I ST CTMU pulse delay input.
INT1 1 I ST External Interrupt 1 input.
RB2/CANTX/C1OUT/
P1C/CTED1/INT2
RB2 0 O DIG LATB<2> data output.
1 I ST PORTB<2> data input; weak pull-up when RBPU bit is cleared.
CANTX
(2)
0 O DIG CAN bus TX.
C1OUT
(1)
0 O DIG Comparator 1 output; takes priority over port data.
P1C
(1)
0 O DIG ECCP1 PWM Output C. May be configured for tri-state during
Enhanced PWM.
CTED1 x I ST CTMU Edge 1 input.
INT2 1 I ST External Interrupt 2.
RB3/CANRX/
C2OUT/P1D/
CTED2/INT3
RB3 0 O DIG LATB<3> data output.
1 I ST PORTB<3> data input; weak pull-up when RBPU bit is cleared.
CANRX
(2)
1 I ST CAN bus RX.
C2OUT
(1)
x I ST CTMU Edge 2 input.
P1D
(1)
0 O DIG ECCP1 PWM Output D. May be configured for tri-state during
Enhanced PWM.
CTED2 x I ST CTMU Edge 2 input.
INT3 1 I ST External Interrupt 3 input.
RB4/AN9/C2INA/
ECCP1/P1A/CTPLS/
KBI0
RB4 0 O DIG LATB<4> data output.
1 I ST PORTB<4> data input; weak pull-up when RBPU bit is cleared.
AN9 1 I ANA A/D Input Channel 9 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
C2INA
(1)
2 I ANA Comparator 2 Input A.
ECCP1
(1)
0 O DIG ECCP1 compare output and ECCP1 PWM output. Takes priority
over port data.
1 I ST ECCP1 capture input.
P1A
(1)
0 O DIG ECCP1 Enhanced PWM output, Channel A. May be configured for
tri-state during Enhanced PWM shutdown events. Takes priority
over port data.
CTPLS x O DIG CTMU pulse generator output.
KBI0 1 I ST Interrupt-on-pin change.
Legend: O = Output, I = Input, ANA = Analog Signal, DIG = CMOS Output, ST = Schmitt Trigger Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option)
Note 1: Pin assignment only available for 28-pin devices (PIC18F2XK80).
2: Default pin assignment for CANRX and CANTX when the CANMX Configuration bit is set.
3: Default pin assignment for T0CKI when the T0CKMX Configuration bit is set.
4: Default pin assignment for T3CKI for 28, 40 and 44-pin devices. Alternate pin assignment for T3CKI for 64-pin devices
when T3CKMX is cleared.