Datasheet

 2009-2018 Microchip Technology Inc. DS30009960F-page 341
PIC18F87K22 FAMILY
22.4.2 EUSART SYNCHRONOUS SLAVE
RECEPTION
The operation of the Synchronous Master and Slave
modes is identical except in the case of Sleep, or any
Idle mode, and bit, SREN, which is a “don’t care” in
Slave mode.
If receive is enabled by setting the CREN bit prior to
entering Sleep or any Idle mode, then a word may be
received while in this low-power mode. Once the word
is received, the RSR register will transfer the data to the
RCREGx register. If the RCxIE enable bit is set, the
interrupt generated will wake the chip from the
low-power mode. If the global interrupt is enabled, the
program will branch to the interrupt vector.
To set up a Synchronous Slave Reception:
1. Enable the synchronous master serial port by
setting bits, SYNC and SPEN, and clearing bit,
CSRC.
2. If interrupts are desired, set enable bit, RCxIE.
3. If 9-bit reception is desired, set bit, RX9.
4. To enable reception, set enable bit, CREN.
5. Flag bit, RCxIF, will be set when reception is
complete. An interrupt will be generated if
enable bit, RCxIE, was set.
6. Read the RCSTAx register to get the 9th bit (if
enabled) and determine if any error occurred
during reception.
7. Read the 8-bit received data by reading the
RCREGx register.
8. If any error occurred, clear the error by clearing
bit, CREN.
9. If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TABLE 22-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF
PIR1
PSPIF ADIF RC1IF TX1IF SSP1IF TMR1GIF TMR2IF TMR1IF
PIE1
PSPIE ADIE RC1IE TX1IE SSP1IE TMR1GIE TMR2IE TMR1IE
IPR1 PSPIP ADIP RC1IP TX1IP SSP1IP TMR1GIP TMR2IP TMR1IP
PIR3
TMR5GIF —RC2IFTX2IF CTMUIF CCP2IF CCP1IF RTCCIF
PIE3
TMR5GIE — RC2IE TX2IE CTMUIE CCP2IE CCP1IE RTCCIE
IPR3 TMR5GIP — RC2IP TX2IP CTMUIP CCP2IP CCP1IP RTCCIP
RCSTA1 SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D
RCREG1 EUSART1 Receive Register
TXSTA1 CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCON1
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGH1 EUSART1 Baud Rate Generator Register High Byte
SPBRG1 EUSART1 Baud Rate Generator Register
RCSTA2 SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D
RCREG2 EUSART2 Receive Register
TXSTA2 CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D
BAUDCON2
ABDOVF RCIDL RXDTP TXCKP BRG16 — WUE ABDEN
SPBRGH2 EUSART2 Baud Rate Generator Register High Byte
SPBRG2 EUSART2 Baud Rate Generator Register
ODCON3 U2OD U1OD
— — — — — CTMUDS
PMD0 CCP3MD CCP2MD CCP1MD UART2MD UART1MD SSP2MD SSP1MD ADCMD
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave reception.