Datasheet

 2010-2015 Microchip Technology Inc. DS40001303H-page 5
PIC18F2XK20/4XK20
FIGURE 5: 44-PIN QFN
FIGURE 6: 44-PIN TQFP
10
11
2
3
4
5
6
1
18 19 20 21 22 12 13 14 15
38
8
7
44 43 42 41 40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34 35
9
37
AN3/V
REF+/C1IN+/RA3
AN2/V
REF-/CVREF/C2IN+/RA2
AN1/C12IN1-/RA1 AN0/C12IN0-/RA0
MCLR
/VPP/RE3
AN9/C12IN2-/CCP2
(1)
/RB3
KBI3/PGD/RB7 KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4
NC
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2
(1)
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V
SS
VSS
VDD
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS
/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
RD4/PSP4/RD4
PSP5/P1B/RD5
PSP6/P1C/RD6
PSP7/P1D/RD7
V
SS
VDD
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: The exposed pad should be connected to V
SS.
3: See Table 2 for pin allocation table.
10
11
2
3
4
5
6
1
18 19 20 21 22 12 13 14 15
38
8
7
44 43 42 41 40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36 34 35
9
37
AN3/VREF+/C1IN+/RA3
AN2/V
REF-/CVREF/C2IN+/RA2
AN1/C12IN1-/RA1 AN0/C12IN0-/RA0
MCLR
/VPP/RE3
NC
KBI3/PGD/RB7 KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4
NC
RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0
RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2
(1)
NC
NC
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V
SS
VDD
RE2/CS/AN7
RE1/WR
/AN6
RE0/RD
/AN5
RA5/AN4/SS
/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
PSP4/RD4
PSP6/P1C/RD6
PSP7/P1D/RD7
V
SS
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
AN9/C12IN2-/CCP2
(1)
/RB3
PIC18F43K20
PIC18F44K20
PIC18F45K20
PIC18F46K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: See Table 2 for pin allocation table.
PSP5/P1B/RD5