Datasheet

PIC18F2XK20/4XK20
DS40001303H-page 4  2010-2015 Microchip Technology Inc.
FIGURE 3: 40-PIN PDIP
FIGURE 4: 40-PIN UQFN
RB7/KBI3/PGD
RB6/KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11
RB3/AN9/C12IN2-/CCP2
(1)
RB2/INT2/AN8
RB1/INT1/AN10/C12IN3-
RB0/INT0/FLT0/AN12
V
DD
VSS
RD7/PSP7/P1D
RD6/PSP6/P1C
RD5/PSP5/P1B
RD4/PSP4
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
RD3/PSP3
RD2/PSP2
MCLR/VPP/RE3
AN0/C12IN0-/RA0
AN1/C12IN1-/RA1
AN2/V
REF-/CVREF/C2IN+/RA2
AN3/V
REF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS
/HLVDIN/C2OUT/RA5
R
D/AN5/RE0
W
R/AN6/RE1
C
S/AN7/RE2
V
DD
VSS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSO/T13CKI/RC0
T1OSI/CCP2
(1)
/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
PSP0/RD0
PSP1/RD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
PIC18F43K20 PIC18F44K20 PIC18F45K20 PIC18F46K20
Note: See Table 2 for pin allocation table.
10
11
2
3
4
5
6
1
18 19 20
21
22
12 13 14 15
38
8
7
40 39
16 17
29
30
31
32
33
23
24
25
26
27
28
36
34
35
9
37
AN1/C12/IN1-/RA1
AN0/C12IN0-/RA0
M
CLR/VPP/RE3
AN9/C12IN2-/CCP/RB3
KBI3/PGD/RB7
KBI2/PGC/RB6
KBI1/PGM/RB5
KBI0/AN11/RB4
RC6/TX/Ck
RC5/SDO
RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RD1/PSP1 RD0/PSP0 RC3/SCK/SCL RC2/CCP1/P1A RC1/T1OSI/CCP2
RC0/T1OSO/T13CKI
RA6/OSC2/CLKOUT
RA7/OSC1/CLKIN
V
SS
VDD
RE2/CS/AN7
RE1/WR/AN6
RE0/RD
/AN5
RA5/AN4/SS
/HLVDIN/C2OUT
RA4/T0CKI/C1OUT
RX/DT/RC7
RD4/PSP4/RD4
PSP5/P1B/RD5
RD6/PSP6/P1C/RD6
PSP7/P1D/RD7
V
SS
VDD
INT0/FLT0/AN12/RB0
INT1/AN10/C12IN3-/RB1
INT2/AN8/RB2
AN3/VREF+/C1IN+/RA3
AN2/V
REF-/CVREF/C2IN+/RA2
PIC18F4XK20
Note 1: See Table 2 for location of all peripheral functions.
2: It is recommended that the exposed bottom pad be connected to V
SS.