Datasheet

 2010-2015 Microchip Technology Inc. DS40001303H-page 379
PIC18F2XK20/4XK20
FIGURE 26-16: I
2
C™ BUS START/STOP BITS TIMING
83 TscH2ssH,
TscL2ssH
SS  after SCK Edge 1.5 TCY + 40 — ns
TABLE 26-29: I
2
C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
90 T
SU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Start condition
Setup Time 400 kHz mode 600 —
91 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
clock pulse is generated
Hold Time 400 kHz mode 600 —
92 T
SU:STO Stop Condition 100 kHz mode 4700 — ns
Setup Time 400 kHz mode 600 —
93 T
HD:STO Stop Condition 100 kHz mode 4000 — ns
Hold Time 400 kHz mode 600 —
TABLE 26-28: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) (CONTINUED)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
Note 1: Requires the use of Parameter #73A.
2: Only if Parameter #71A and #72A are used.
Note: Refer to Figure 26-4 for load conditions.
91
92
93
SCL
SDA
Start
Condition
Stop
Condition
90