Datasheet

PIC18F2XK20/4XK20
DS40001303H-page 374  2010-2015 Microchip Technology Inc.
FIGURE 26-11: PARALLEL SLAVE PORT TIMING (PIC18F4XK20)
TABLE 26-23: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
50 TccL CCPx Input Low
Time
No prescaler 0.5 T
CY + 20 — ns
With
prescaler
10 — ns
51 TccH CCPx Input
High Time
No prescaler 0.5 T
CY + 20 — ns
With
prescaler
10 — ns
52 TccP CCPx Input Period 3 T
CY + 40
N
— ns N = prescale
value (1, 4 or
16)
53 TccR CCPx Output Fall Time — 25 ns
54 TccF CCPx Output Fall Time — 25 ns
TABLE 26-24: PARALLEL SLAVE PORT REQUIREMENTS (PIC18F4XK20)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
62 TdtV2wrH Data In Valid before WR
 or CS 
(setup time)
20 — ns
63 TwrH2dtI WR
 or CS  to Data–In Invalid (hold time) 20 — ns
64 TrdL2dtV RD
 and CS  to Data–Out Valid — 80 ns
65 TrdH2dtI RD
 or CS  to Data–Out Invalid 10 30 ns
66 TibfINH Inhibit of the IBF Flag bit being cleared from
WR
 or CS 
—3 T
CY
Note: Refer to Figure 26-4 for load conditions.
RE2/CS
RE0/RD
RE1/WR
RD7:RD0
62
63
64
65