Datasheet

PIC18F2XK20/4XK20
DS40001303H-page 372  2010-2015 Microchip Technology Inc.
FIGURE 26-9: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS
TABLE 26-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET REQUIREMENTS
Param.
No.
Symbol Characteristic Min. Typ. Max. Units Conditions
30 TmcL MCLR
Pulse Width (low) 2 — — s
31 T
WDT Watchdog Timer Time-out Period
(no postscaler)
3.5 4.1 4.7 ms 1:1 prescaler
32 T
OST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC —TOSC = OSC1 period
33 T
PWRT Power-up Timer Period 54.8 64.4 74.1 ms
34 T
IOZ I/O High-Impedance from MCLR
Low or Watchdog Timer Reset
—2—s
35 T
BOR Brown-out Reset Pulse Width 200 — — sVDD  BVDD (see
D005)
36 T
IVRST Internal Reference Voltage Stable — 25 35 s
37 THLVD High/Low-Voltage Detect Pulse
Width
200 — — sVDD  VHLVD
38 TCSD CPU Start-up Time 5 — 10 s
39 TIOBST Time for HF-INTOSC to Stabilize — 0.25 1 ms
Note: Refer to Figure 26-4 for load conditions.
46
47
45
48
41
42
40
T0CKI
T1OSO/T13CKI
TMR0 or
TMR1