Datasheet

PIC18F2XK20/4XK20
DS40001303H-page 180  2010-2015 Microchip Technology Inc.
17.0 MASTER SYNCHRONOUS
SERIAL PORT (MSSP)
MODULE
17.1 Master SSP (MSSP) Module
Overview
The Master Synchronous Serial Port (MSSP) module is
a serial interface, useful for communicating with other
peripheral or microcontroller devices. These peripheral
devices may be serial EEPROMs, shift registers,
display drivers, A/D converters, etc. The MSSP module
can operate in one of two modes:
• Serial Peripheral Interface (SPI)
• Inter-Integrated Circuit (I
2
C)
- Full Master mode
- Slave mode (with general address call)
The I
2
C interface supports the following modes in
hardware:
•Master mode
• Multi-Master mode
• Slave mode
17.2 Control Registers
The MSSP module has seven associated registers.
These include:
• SSPSTA – STATUS register
• SSPCON1 – First Control register
• SSPCON2 – Second Control register
• SSPBUF – Transmit/Receive buffer
• SSPSR – Shift register (not directly accessible)
• SSPADD – Address register
• SSPMSK – Address Mask register
The use of these registers and their individual Configu-
ration bits differ significantly depending on whether the
MSSP module is operated in SPI or I
2
C mode.
Additional details are provided under the individual
sections.
17.3 SPI Mode
The SPI mode allows eight bits of data to be
synchronously transmitted and received
simultaneously. All four modes of SPI are supported. To
accomplish communication, typically three pins are
used:
• Serial Data Out – SDO
• Serial Data In – SDI/SDA
• Serial Clock – SCK/SCL
Additionally, a fourth pin may be used when in a Slave
mode of operation:
• Slave Select – SS
Figure 17-1 shows the block diagram of the MSSP
module when operating in SPI mode.
FIGURE 17-1: MSSP BLOCK DIAGRAM
(SPI MODE)
( )
Read Write
Internal
Data Bus
SSPSR Reg
SSPM<3:0>
bit 0
Shift
Clock
SS
Control
Enable
Edge
Select
Clock Select
TMR2 Output
T
OSC
Prescaler
4, 16, 64
2
Edge
Select
2
4
Data to TX/RX in SSPSR
TRIS bit
2
SMP:CKE
SDO
SSPBUF Reg
SDI/SDA
SS
SCK/SCL