Datasheet

PIC18F2480/2580/4480/4580
DS39637A-page 58 Preliminary  2004 Microchip Technology Inc.
B2CON
(6)
2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu
B1D7
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D6
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D5
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D4
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D3
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D2
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D1
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1D0
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1DLC
(6)
2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu
B1EIDL
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1EIDH
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1SIDL
(6)
2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu
B1SIDH
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B1CON
(6)
2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu
B0D7
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D6
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D5
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D4
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D3
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D2
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D1
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0D0
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0DLC
(6)
2480 2580 4480 4580 -xxx xxxx -uuu uuuu -uuu uuuu
B0EIDL
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0EIDH
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0SIDL
(6)
2480 2580 4480 4580 xxxx x-xx uuuu u-uu uuuu u-uu
B0SIDH
(6)
2480 2580 4480 4580 xxxx xxxx uuuu uuuu uuuu uuuu
B0CON
(6)
2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu
TXBIE
(6)
2480 2580 4480 4580 ---0 00-- ---u uu-- ---u uu--
BIE0
(6)
2480 2580 4480 4580 0000 0000 0000 0000 uuuu uuuu
TABLE 4-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)
Register Applicable Devices
Power-on Reset,
Brown-out Reset
MCLR
Resets,
WDT Reset,
RESET Instruction,
Stack Resets
Wake-up via WDT
or Interrupt
Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.
Shaded cells indicate conditions do not apply for the designated device.
Note 1: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt
vector (0008h or 0018h).
3: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are
updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.
4: See Table 4-3 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled, depending on the oscillator mode selected. When
not enabled as PORTA pins, they are disabled and read ‘0’.
6: This register reads all ‘0’s until ECAN™ technology is set up in Mode 1 or Mode 2.