Datasheet

PIC18F2480/2580/4480/4580
DS39637A-page 470 Preliminary  2004 Microchip Technology Inc.
Electrical Characteristics ..................................................417
Enhanced Capture/Compare/PWM (ECCP) ....................173
Capture Mode. See Capture (ECCP Module).
Outputs and Configuration .......................................174
Pin Configurations for ECCP1 .................................174
PWM Mode. See PWM (ECCP Module).
Timer Resources ......................................................174
Enhanced PWM Mode. See PWM (ECCP Module).
Enhanced Universal Synchronous Receiver
Transmitter (EUSART). See EUSART.
Equations
A/D Acquisition Time ................................................252
A/D Minimum Charging Time ...................................252
Errata ...................................................................................5
Error Recognition Mode ...................................................324
EUSART
Asynchronous Mode ................................................236
Associated Registers, Receive ........................ 239
Associated Registers, Transmit .......................237
Auto-Wake-up on Sync Break ..........................240
Break Character Sequence ..............................241
Receiver ...........................................................238
Setting up 9-Bit Mode with
Address Detect ........................................238
Transmitter .......................................................236
Baud Rate Generator (BRG)
Associated Registers .......................................231
Auto-Baud Rate Detect ....................................234
Baud Rate Error, Calculating ...........................231
Baud Rates, Asynchronous Modes ..................232
High Baud Rate Select (BRGH Bit) ..................231
Operation in Power Managed Mode ................231
Sampling ..........................................................231
Synchronous Master Mode ......................................242
Associated Registers, Receive ........................ 244
Associated Registers, Transmit .......................243
Reception .........................................................244
Transmission ....................................................242
Synchronous Slave Mode ........................................245
Associated Registers, Receive ........................ 246
Associated Registers, Transmit .......................245
Reception .........................................................246
Transmission ....................................................245
Evaluation and Programming Tools .................................415
Extended Instruction Set
ADDFSR ..................................................................404
ADDULNK ................................................................404
CALLW .....................................................................405
MOVSF ....................................................................405
MOVSS ....................................................................406
PUSHL .....................................................................406
SUBFSR ..................................................................407
SUBULNK ................................................................407
External Clock Input ...........................................................24
F
Fail-Safe Clock Monitor ............................................343, 355
Interrupts in Power Managed Modes .......................356
POR or Wake-up from Sleep ...................................356
WDT During Oscillator Failure .................................355
Fast Register Stack ............................................................64
Firmware Instructions .......................................................361
Flash Program Memory ..................................................... 95
Associated Registers ............................................... 103
Control Registers ....................................................... 96
EECON1 and EECON2 ..................................... 96
TABLAT (Table Latch) Register ........................ 98
TBLPTR (Table Pointer) Register ...................... 98
Erase Sequence ...................................................... 100
Erasing .................................................................... 100
Operation During Code-Protect ............................... 103
Reading ..................................................................... 99
Table Pointer
Boundaries Based on Operation ....................... 98
Table Pointer Boundaries .......................................... 98
Table Reads and Table Writes .................................. 95
Write Sequence ....................................................... 101
Writing To ................................................................ 101
Protection Against Spurious Writes ................. 103
Unexpected Termination ................................. 103
Write Verify ...................................................... 103
FSCM. See Fail-Safe Clock Monitor.
G
GOTO .............................................................................. 382
H
Hardware Multiplier .......................................................... 111
Introduction .............................................................. 111
Operation ................................................................. 111
Performance Comparison ........................................ 111
High/Low-Voltage Detect ................................................. 267
Applications ............................................................. 270
Characteristics ......................................................... 431
Current Consumption ............................................... 269
Effects of a Reset .................................................... 271
Operation
Associated Registers ....................................... 271
During Sleep .................................................... 271
Setup ....................................................................... 269
Start-up Time ........................................................... 269
Typical Application ................................................... 270
HLVD. See High/Low-Voltage Detect.
I
I/O Ports ........................................................................... 129
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2
C Mode (MSSP)
Acknowledge Sequence Timing .............................. 220
Baud Rate Generator .............................................. 213
Bus Collision
During a Repeated Start Condition .................. 224
During a Stop Condition .................................. 225
Clock Arbitration ...................................................... 214
Clock Stretching ....................................................... 206
10-Bit Slave Receive Mode (SEN = 1) ............ 206
10-Bit Slave Transmit Mode ............................ 206
7-Bit Slave Receive Mode (SEN = 1) .............. 206
7-Bit Slave Transmit Mode .............................. 206
Clock Synchronization and the
CKP Bit (SEN = 1) ........................................... 207
Effect of a Reset ...................................................... 221
General Call Address Support ................................. 210
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2
C Clock Rate w/BRG ............................................. 213