Datasheet

DS39631E-page 399 © 2008 Microchip Technology Inc.
PIC18F2420/2520/4420/4520
DC Characteristics ............................................................335
Power-Down and Supply Current..............................325
Supply Voltage .......................................................... 324
DCFSNZ............................................................................287
DECF.................................................................................286
DECFSZ............................................................................287
Development Support........................................................ 317
Device Differences ............................................................395
Device Overview ...................................................................7
Details on Individual Family Members ..........................8
Features (table).............................................................9
New Core Features .......................................................7
Other Special Features .................................................8
Device Reset Timers...........................................................45
Oscillator Start-up Timer (OST) ..................................45
PLL Lock Time-out ......................................................45
Power-up Timer (PWRT).............................................45
Time-out Sequence .....................................................45
Direct Addressing ................................................................69
E
Effect on Standard PIC MCU Instructions .........................314
Effects of Power-Managed Modes on
Various Clock Sources................................................31
Electrical Characteristics ...................................................321
Enhanced Capture/Compare/PWM (ECCP) .....................147
Associated Registers ................................................160
Capture and Compare Modes...................................148
Capture Mode.
See Capture (ECCP Module).
Outputs and Configuration ........................................148
Pin Configurations for ECCP.....................................148
PWM Mode.
See PWM (ECCP Module).
Standard PWM Mode................................................148
Timer Resources.......................................................148
Enhanced PWM Mode.
See PWM (ECCP Module).
Enhanced Universal Synchronous Asynchronous
Receiver Transmitter (EUSART).
See EUSART.
Equations
A/D Acquisition Time.................................................228
A/D Minimum Charging Time ....................................228
Calculating the Minimum Required
Acquisition Time................................................228
Errata.....................................................................................6
EUSART
Asynchronous Mode .................................................211
12-Bit Break Transmit and Receive ..................216
Associated Registers, Receive ......................... 214
Associated Registers, Transmit ........................ 212
Auto-Wake-up on Sync Break...........................214
Receiver............................................................213
Setting up 9-Bit Mode with
Address Detect .........................................213
Transmitter ........................................................211
Baud Rate Generator
Operation in Power-Managed Mode .................205
Baud Rate Generator (BRG)..................................... 205
Associated Registers ........................................206
Auto-Baud Rate Detect ..................................... 209
Baud Rate Error, Calculating ............................206
Baud Rates, Asynchronous Modes................... 207
High Baud Rate Select (BRGH Bit)................... 205
Sampling ...........................................................205
Synchronous Master Mode....................................... 217
Associated Registers, Receive......................... 219
Associated Registers, Transmit ........................ 218
Reception.......................................................... 219
Transmission .................................................... 217
Synchronous Slave Mode ......................................... 220
Associated Registers, Receive......................... 221
Associated Registers, Transmit ........................ 220
Reception.......................................................... 221
Transmission .................................................... 220
Extended Instruction Set
ADDFSR ................................................................... 310
ADDULNK................................................................. 310
and Using MPLAB IDE Tools.................................... 316
CALLW ..................................................................... 311
Considerations for Use ............................................. 314
MOVSF ..................................................................... 311
MOVSS..................................................................... 312
PUSHL...................................................................... 312
SUBFSR ................................................................... 313
SUBULNK................................................................. 313
Syntax....................................................................... 309
External Clock Input............................................................ 24
F
Fail-Safe Clock Monitor............................................. 249, 261
Exiting Operation ...................................................... 261
Interrupts in Power-Managed Modes........................ 262
POR or Wake from Sleep ......................................... 262
WDT During Oscillator Failure .................................. 261
Fast Register Stack............................................................. 56
Firmware Instructions........................................................ 267
Flash Program Memory ...................................................... 73
Associated Registers .................................................. 81
Control Registers ........................................................ 74
EECON1 and EECON2 ...................................... 74
TABLAT (Table Latch) Register.......................... 76
TBLPTR (Table Pointer) Register....................... 76
Erase Sequence ......................................................... 78
Erasing........................................................................ 78
Operation During Code-Protect .................................. 81
Reading ...................................................................... 77
Table Pointer
Boundaries Based on Operation......................... 76
Table Pointer Boundaries ........................................... 76
Table Reads and Table Writes ................................... 73
Write Sequence .......................................................... 79
Writing To ................................................................... 79
Protection Against Spurious Writes .................... 81
Unexpected Termination..................................... 81
Write Verify ......................................................... 81
FSCM.
See Fail-Safe Clock Monitor.
G
General Call Address Support .......................................... 184
GOTO ............................................................................... 288
H
Hardware Multiplier ............................................................. 89
Introduction ................................................................. 89
Operation .................................................................... 89
Performance Comparison........................................... 89