Datasheet

© 2008 Microchip Technology Inc. DS39631E-page 357
PIC18F2420/2520/4420/4520
FIGURE 26-21: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
TABLE 26-22: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Param
No.
Symbol Characteristic Min Max Units Conditions
120 TckH2dtV SYNC XMIT (MASTER & SLAVE)
Clock High to Data Out Valid PIC18FXXXX — 40 ns
PIC18LFXXXX — 100 ns VDD = 2.0V
121 Tckrf Clock Out Rise Time and Fall Time
(Master mode)
PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns V
DD = 2.0V
122 Tdtrf Data Out Rise Time and Fall Time PIC18FXXXX — 20 ns
PIC18LFXXXX — 50 ns VDD = 2.0V
121
121
120
122
RC6/TX/CK
RC7/RX/DT
pin
pin
Note: Refer to Figure 26-5 for load conditions.