Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 136  2010-2016 Microchip Technology Inc.
TABLE 10-6: REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150
ECCP2AS
CCP2ASE CCP2AS<2:0> PSS2AC<1:0> PSS2BD<1:0>
202
CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 198
ECCP3AS
CCP3ASE CCP3AS<2:0> PSS3AC<1:0> PSS3BD<1:0>
202
CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 198
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109
INTCON2 R
BPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP —RBIP110
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 111
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— — — — 153
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 152
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 148
SLRCON
— — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 153
T1GCON TMR1GE
T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 167
T3CON TMR3CS<1:0>
T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 166
T5GCON TMR5GE
T5GPOL T5GTM T5GSPM T5GGO/DONE T5GVAL T5GSS<1:0> 167
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 151
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 152
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Note 1: Available on PIC18(L)F4XK22 devices.
TABLE 10-7: CONFIGURATION REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CONFIG3H
MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348
CONFIG4L DEBUG
XINST — — —LVP
(1)
— STRVEN 349
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Note 1: Can only be changed when in high voltage programming mode.