Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 126  2010-2016 Microchip Technology Inc.
TABLE 9-1: REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 150
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 109
INTCON2 R
BPU INTEDG0 INTEDG1 INTEDG2 —TMR0IP —RBIP110
INTCON3 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF 111
IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 153
IPR1
— ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 121
IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 122
IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP 123
IPR4
— — — — — CCP5IP CCP4IP CCP3IP 124
IPR5 — — — — — TMR6IP TMR5IP TMR4IP 124
PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 117
PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 118
PIE3 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE 119
PIE4
— — — — — CCP5IE CCP4IE CCP3IE 120
PIE5
— — — — — TMR6IE TMR5IE TMR4IE 120
PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 112
PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 113
PIR3 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF 114
PIR4
— — — — — CCP5IF CCP4IF CCP3IF 115
PIR5 — — — — — TMR6IF TMR5IF TMR4IF 116
PORTB RB7 RB6 RB5 RB4
RB3 RB2 RB1 RB0 148
RCON IPEN SBOREN — RI TO PD POR BOR 56
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.
TABLE 9-2: CONFIGURATION REGISTERS ASSOCIATED WITH INTERRUPTS
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CONFIG3H
MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 348
CONFIG4L
DEBUG XINST — — — LVP — STRVEN 349
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts.