Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 208  2010-2016 Microchip Technology Inc.
FIGURE 15-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION
15.2.1 SPI MODE REGISTERS
The MSSPx module has five registers for SPI mode
operation. These are:
• MSSPx STATUS register (SSPxSTAT)
• MSSPx Control register 1 (SSPxCON1)
• MSSPx Control register 3 (SSPxCON3)
• MSSPx Data Buffer register (SSPxBUF)
• MSSPx Address register (SSPxADD)
• MSSPx Shift register (SSPxSR)
(Not directly accessible)
SSPxCON1 and SSPxSTAT are the control and
STATUS registers in SPI mode operation. The
SSPxCON1 register is readable and writable. The
lower 6 bits of the SSPxSTAT are read-only. The upper
two bits of the SSPxSTAT are read/write.
In one SPI Master mode, SSPxADD can be loaded
with a value used in the Baud Rate Generator. More
information on the Baud Rate Generator is available in
Section 15.7 “Baud Rate Generator”.
SSPxSR is the shift register used for shifting data in
and out. SSPxBUF provides indirect access to the
SSPxSR register. SSPxBUF is the buffer register to
which data bytes are written, and from which data
bytes are read.
In receive operations, SSPxSR and SSPxBUF
together create a buffered receiver. When SSPxSR
receives a complete byte, it is transferred to SSPxBUF
and the SSPxIF interrupt is set.
During transmission, the SSPxBUF is not buffered. A
write to SSPxBUF will write to both SSPxBUF and
SSPxSR.
15.2.2 SPI MODE OPERATION
When initializing the SPI, several options need to be
specified. This is done by programming the appropriate
control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>).
These control bits allow the following to be specified:
• Master mode (SCKx is the clock output)
• Slave mode (SCKx is the clock input)
• Clock Polarity (Idle state of SCKx)
• Data Input Sample Phase (middle or end of data
output time)
• Clock Edge (output data on rising/falling edge of
SCKx)
• Clock Rate (Master mode only)
• Slave Select mode (Slave mode only)
To enable the serial port, SSPx Enable bit, SSPxEN of
the SSPxCON1 register, must be set. To reset or
reconfigure SPI mode, clear the SSPxEN bit,
re-initialize the SSPxCONx registers and then set the
SSPxEN bit. This configures the SDIx, SDOx, SCKx
and SSx
pins as serial port pins. For the pins to behave
as the serial port function, some must have their data
direction bits (in the TRIS register) appropriately
programmed as follows:
• SDIx must have corresponding TRIS bit set
• SDOx must have corresponding TRIS bit cleared
• SCKx (Master mode) must have corresponding
TRIS bit cleared
• SCKx (Slave mode) must have corresponding
TRIS bit set
• SSx
must have corresponding TRIS bit set
SPI Master
SCLK
SDOx
SDIx
General I/O
General I/O
General I/O
SCLK
SDIx
SDOx
SSx
SPI Slave
#1
SCLK
SDIx
SDOx
SSx
SPI Slave
#2
SCLK
SDIx
SDOx
SSx
SPI Slave
#3