Datasheet

PIC18(L)F2X/4XK22
DS40001412G-page 128  2010-2016 Microchip Technology Inc.
TABLE 10-1: PORTA I/O SUMMARY
Pin Name Function
TRIS
Setting
ANSEL
Setting
Pin
Type
Buffer
Type
Description
RA0/C12IN0-/AN0 RA0 00O DIG LATA<0> data output; not affected by analog input.
10I TTL PORTA<0> data input; disabled when analog input enabled.
C12IN0- 11I AN Comparators C1 and C2 inverting input.
AN0 11I AN Analog input 0.
RA1/C12IN1-/AN1 RA1 00O DIG LATA<1> data output; not affected by analog input.
10I TTL PORTA<1> data input; disabled when analog input enabled.
C12IN1- 11I AN Comparators C1 and C2 inverting input.
AN1 11I AN Analog input 1.
RA2/C2IN+/AN2/
DACOUT/V
REF-
RA2 00O DIG LATA<2> data output; not affected by analog input; disabled when
DACOUT enabled.
10I TTL PORTA<2> data input; disabled when analog input enabled;
disabled when DACOUT enabled.
C2IN+ 11I AN Comparator C2 non-inverting input.
AN2 11I AN Analog output 2.
DACOUT x1O AN DAC Reference output.
V
REF- 11I AN A/D reference voltage (low) input.
RA3/C1IN+/AN3/
V
REF+
RA3 0 O DIG LATA<3> data output; not affected by analog input.
10I TTL PORTA<3> data input; disabled when analog input enabled.
C1IN+ 11I AN Comparator C1 non-inverting input.
AN3 11I AN Analog input 3.
V
REF+ 11I AN A/D reference voltage (high) input.
RA4/CCP5/C1OUT/
SRQ/T0CKI
RA4 0 — O DIG LATA<4> data output.
1 — I ST PORTA<4> data input; default configuration on POR.
CCP5 0 — O DIG CCP5 Compare output/PWM output, takes priority over RA4 output.
1 — I ST Capture 5 input/Compare 5 output/ PWM 5 output.
C1OUT 0 — O DIG Comparator C1 output.
SRQ 0 — O DIG SR latch Q output; take priority over CCP 5 output.
T0CKI 1 — I ST Timer0 external clock input.
RA5/C2OUT/SRNQ/
SS1
/
HLVDIN/AN4
RA5 00O DIG LATA<5> data output; not affected by analog input.
10I TTL PORTA<5> data input; disabled when analog input enabled.
C2OUT 00O DIG Comparator C2 output.
SRNQ 00O DIG SR latch Q
output.
SS1
10I TTL SPI slave select input (MSSP1).
HLVDIN 11I AN High/Low-Voltage Detect input.
AN4 11I AN A/D input 4.
RA6/CLKO/OSC2 RA6 0 — O DIG LATA<6> data output; enabled in INTOSC modes when CLKO is not
enabled.
1 — I TTL PORTA<6> data input; enabled in INTOSC modes when CLKO is
not enabled.
CLKO x — O DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the fre-
quency of OSC1 and denotes the instruction cycle rate.
OSC2 x — O XTAL Oscillator crystal output; connects to crystal or resonator in Crystal
Oscillator mode.
RA7/CLKI/OSC1 RA7 0 — O DIG LATA<7> data output; disabled in external oscillator modes.
1 — I TTL PORTA<7> data input; disabled in external oscillator modes.
CLKI x — I AN External clock source input; always associated with pin function
OSC1.
OSC1 x — I XTAL Oscillator crystal input or external clock source input ST buffer when
configured in RC mode; CMOS otherwise.
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS = CMOS
compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C = Schmitt Trigger input with I
2
C.