Datasheet

 2010-2015 Microchip Technology Inc. DS40001303H-page 3
PIC18F2XK20/4XK20
Pin Diagrams
FIGURE 1: 28-PIN SPDIP, SOIC, SSOP
FIGURE 2: 28-PIN QFN/UQFN
10
11
2
3
4
5
6
1
8
7
9
12
13
14
15
16
17
18
19
20
23
24
25
26
27
28
22
21
MCLR/VPP/RE3
AN0/C12IN0-/RA0
AN1/C12IN1-/RA1
AN2/V
REF-/CVREF/C2IN+/RA2
AN3/V
REF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS
/HLVDIN/C2OUT/RA5
V
SS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSO/T13CKI/RC0
T1OSI/CCP2
(1)
/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
RB7/KBI3/PGD
RB6//KBI2/PGC
RB5/KBI1/PGM
RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2
(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V
DD
VSS
RC7/RX/DT
RC6/TX/CK
RC5/SDO
RC4/SDI/SDA
PIC18F23K20 PIC18F24K20 PIC18F25K20 PIC18F26K20
Note: See Table 1 for pin allocation table.
1011
2
3
6
1
18
19
20
21
22
121314
15
8
7
16
17
232425262728
9
T1OSO/T13CKI/RC0
5
4
RB7/KBI3/PGD RB6/KBI2/PGC RB5/KBI1/PGM RB4/KBI0/AN11/P1D
RB3/AN9/C12IN2-/CCP2
(1)
RB2/INT2/AN8/P1B
RB1/INT1/AN10/C12IN3-/P1C
RB0/INT0/FLT0/AN12
V
DD
VSS
RC7/RX/DT
TX/CK/RC6
SDO/RC5
SDI/SDA/RC4
RE3/
MCLR/VPP
RA0/AN0/C12IN0- RA1/AN1/C12IN1-
AN2/VREF-/CVREF/C2IN+/RA2
AN3/V
REF+/C1IN+/RA3
T0CKI/C1OUT/RA4
AN4/SS
/HLVDIN/C2OUT/RA5
V
SS
OSC1/CLKIN/RA7
OSC2/CLKOUT/RA6
T1OSI/CCP2
(1)
/RC1
CCP1/P1A/RC2
SCK/SCL/RC3
PIC18F23K20
PIC18F24K20
PIC18F25K20
PIC18F26K20
Note 1: RB3 is the alternate pin for CCP2 multiplexing.
2: UQFN package availability applies only to PIC18F23K20.
3: See Table 1 for pin allocation table.
4: The exposed pad should be connected to V
SS.