Datasheet

PIC18F2XK20/4XK20
DS40001303H-page 246  2010-2015 Microchip Technology Inc.
FIGURE 18-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)
TABLE 18-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 56
PIR1
PSPIF
(1)
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 59
PIE1 PSPIE
(1)
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 59
IPR1 PSPIP
(1)
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 59
RCSTA SPEN RX9 SREN CREN
ADDEN FERR OERR RX9D 58
RCREG EUSART Receive Register 58
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 58
BAUDCON
ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 58
SPBRGH EUSART Baud Rate Generator Register, High Byte 58
SPBRG EUSART Baud Rate Generator Register, Low Byte 58
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for synchronous master reception.
Note 1: Reserved in 28-pin devices; always maintain these bits clear.
CREN bit
RX/DT
Write to
bit SREN
SREN bit
RCIF bit
(Interrupt)
Read
RXREG
‘0’
bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7
‘0’
Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TX/CK pin
TX/CK pin
pin
(SCKP = 0)
(SCKP = 1)