Datasheet

 2010 Microchip Technology Inc. Preliminary DS41412C-page 55
PIC18(L)F2X/4XK22
TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE
(BY CLOCK SOURCES)
Clock Source
before Wake-up
Clock Source
after Wake-up
Exit Delay
Clock Ready Status
Bit (OSCCON)
Primary Device Clock
(PRI_IDLE mode)
LP, XT, HS
T
CSD
(1)
OSTSHSPLL
EC, RC
HFINTOSC
(2)
IOSF
T1OSC or LFINTOSC
(1)
LP, XT, HS TOST
(3)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
TIOBST
(4)
IOSF
HFINTOSC
(2)
LP, XT, HS TOST
(4)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
None IOSF
None
(Sleep mode)
LP, XT, HS TOST
(3)
OSTSHSPLL TOST + t
PLL
(3)
EC, RC TCSD
(1)
HFINTOSC
(1)
TIOBST
(4)
IOSF
Note 1: T
CSD is a required delay when waking from Sleep and all Idle modes and runs concurrently with any other
required delays (see Section 3.4 “Idle Modes”). On Reset, HFINTOSC defaults to 1 MHz.
2: Includes both the HFINTOSC 16 MHz source and postscaler derived frequencies.
3: TOST is the Oscillator Start-up Timer. t
PLL
is the PLL Lock-out Timer.
4: Execution continues during the HFINTOSC stabilization period, TIOBST.