Datasheet

PIC18(L)F2X/4XK22
DS41412C-page 490 Preliminary  2010 Microchip Technology Inc.
Operation ................................................................. 162
Operation During Sleep ........................................... 166
Oscillator ..................................................................163
Prescaler .................................................................. 163
Timer1 Gate
Selecting Source .............................................. 164
TMR1H Register ......................................................161
TMR1L Register ....................................................... 161
Timer2
Associated registers ................................................. 176
Timer2/4/6 ........................................................................173
Associated registers ................................................. 176
Timers
Timer1
T1CON .............................................................170
T1GCON .......................................................... 171
Timer2/4/6
TXCON ............................................................ 175
Timing Diagrams
A/D Conversion ........................................................ 459
Acknowledge Sequence .......................................... 246
Asynchronous Reception ......................................... 271
Asynchronous Transmission .................................... 266
Asynchronous Transmission (Back to Back) ........... 267
Auto Wake-up Bit (WUE) During Normal Operation 281
Auto Wake-up Bit (WUE) During Sleep ...................281
Automatic Baud Rate Calculator .............................. 280
Baud Rate Generator with Clock Arbitration ............ 239
BRG Reset Due to SDA Arbitration During Start
Condition .......................................................... 250
Brown-out Reset (BOR) ...........................................446
Bus Collision During a Repeated Start Condition
(Case 1) ........................................................... 251
Bus Collision During a Repeated Start Condition
(Case 2) ........................................................... 251
Bus Collision During a Start Condition (SCL = 0) .... 250
Bus Collision During a Stop Condition (Case 1) ...... 252
Bus Collision During a Stop Condition (Case 2) ...... 252
Bus Collision During Start Condition (SDA only) .....249
Bus Collision for Transmit and Acknowledge ........... 248
Capture/Compare/PWM (CCP) ................................448
CLKO and I/O .......................................................... 445
Clock Synchronization ............................................. 236
Clock/Instruction Cycle .............................................. 74
Comparator Output .................................................. 305
EUSART Synchronous Receive (Master/Slave) ...... 458
EUSART Synchronous Transmission
(Master/Slave) .................................................. 458
Example SPI Master Mode (CKE = 0) ..................... 449
Example SPI Master Mode (CKE = 1) ..................... 450
Example SPI Master Mode Timing .......................... 449
Example SPI Slave Mode (CKE = 0) ....................... 451
Example SPI Slave Mode (CKE = 1) ....................... 452
External Clock (All Modes except PLL) .................... 443
Fail-Safe Clock Monitor (FSCM) ................................ 45
First Start Bit Timing ................................................240
Full-Bridge PWM Output .......................................... 193
Half-Bridge PWM Output ................................. 191, 197
High/Low-Voltage Detect Characteristics ................ 440
High-Voltage Detect Operation (VDIRMAG = 1) ...... 346
I
2
C Bus Data ............................................................ 454
I
2
C Bus Start/Stop Bits ............................................. 453
I
2
C Master Mode (7 or 10-Bit Transmission) ........... 243
I
2
C Master Mode (7-Bit Reception) .......................... 245
I
2
C Stop Condition Receive or Transmit Mode ........ 247
Internal Oscillator Switch Timing ............................... 43
Low-Voltage Detect Operation (VDIRMAG = 0) ...... 345
Master SSP I
2
C Bus Data ........................................ 456
Master SSP I
2
C Bus Start/Stop Bits ........................ 456
PWM Auto-shutdown ............................................... 196
Firmware Restart ............................................. 196
PWM Direction Change ........................................... 194
PWM Direction Change at Near 100% Duty Cycle .. 195
PWM Output (Active-High) ...................................... 189
PWM Output (Active-Low) ....................................... 190
Repeat Start Condition ............................................ 241
Reset, Watchdog Timer (WDT), Oscillator Start-up
Timer (OST), Power-up Timer (PWRT) ........... 446
Send Break Character Sequence ............................ 282
Slow Rise Time (MCLR
Tied to VDD,
V
DD Rise > TPWRT) ............................................ 65
SPI Mode (Master Mode) ......................................... 213
Synchronous Reception (Master Mode, SREN) ...... 287
Synchronous Transmission ..................................... 284
Synchronous Transmission (Through TXEN) .......... 284
Time-out Sequence on POR w/PLL Enabled
(MCLR
Tied to VDD) .......................................... 66
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD, Case 1) ................................... 64
Time-out Sequence on Power-up (MCLR
Not Tied to V
DD, Case 2) ................................... 65
Time-out Sequence on Power-up (MCLR
Tied to V
DD, VDD Rise < TPWRT) ....................... 64
Timer0 and Timer1 External Clock .......................... 447
Timer1 Incrementing Edge ...................................... 167
Transition for Entry to SEC_RUN Mode .................... 49
Transition for Entry to Sleep Mode ............................ 51
Transition for Wake from Sleep (HSPLL) .................. 52
Transition from RC_RUN Mode to PRI_RUN Mode .. 50
Transition from SEC_RUN Mode to PRI_RUN
Mode (HSPLL) ................................................... 49
Transition Timing for Entry to Idle Mode .................... 52
Transition Timing for Wake from Idle to Run Mode ... 53
Timing Diagrams and Specifications ............................... 443
A/D Conversion Requirements ................................ 460
Capture/Compare/PWM Requirements ................... 449
CLKO and I/O Requirements ................................... 445
EUSART Synchronous Receive Requirements ....... 458
EUSART Synchronous Transmission Requirements ....
458
Example SPI Mode Requirements
(Master Mode, CKE = 0) .................................. 450
(Master Mode, CKE = 1) .................................. 451
(Slave Mode, CKE = 0) .................................... 452
(Slave Mode, CKE = 1) .................................... 453
External Clock Requirements .................................. 443
I
2
C Bus Data Requirements (Slave Mode) .............. 455
I
2
C Bus Start/Stop Bits Requirements
(Slave Mode) ................................................... 454
Master SSP I
2
C Bus Data Requirements ................ 457
Master SSP I
2
C Bus Start/Stop Bits Requirements . 456
PLL Clock ................................................................ 444
Reset, Watchdog Timer, Oscillator Start-up Timer,
Power-up Timer and Brown-out
Reset Requirements ........................................ 447
Timer0 and Timer1 External Clock Requirements ... 448
Top-of-Stack Access .......................................................... 71
TSTFSZ ........................................................................... 407
Two-Speed Clock Start-up Mode ....................................... 42
Two-Speed Start-up ......................................................... 349