Datasheet

PIC18(L)F2X/4XK22

DS41412C-page 458 Preliminary  2010 Microchip Technology Inc.

FIGURE 27-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

FIGURE 27-20: EUSART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

121

120

122

TXx/CKx

RXx/DTx

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-21: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param.

No.

Symbol Characteristic Min Max Units Conditions

120 TckH2dtV SYNC XMIT (MASTER & SLAVE)

Clock High to Data Out Valid — 40 ns

121 Tckrf Clock Out Rise Time and Fall Time

(Master mode)

—20ns

122 Tdtrf Data Out Rise Time and Fall Time — 20 ns

125

126

TXx/CKx

RXx/DTx

Note: Refer to Figure 27-4 for load conditions.

TABLE 27-22: EUSART SYNCHRONOUS RECEIVE REQUIREMENTS

Param.

No.

Symbol Characteristic Min Max Units Conditions

125 TdtV2ckl SYNC RCV (MASTER & SLAVE)

Data Setup before CK  (DT setup time) 10 — ns

126 TckL2dtl Data Hold after CK  (DT hold time) 15 — ns