Datasheet

 2010 Microchip Technology Inc. Preliminary DS41412C-page 201
PIC18(L)F2X/4XK22
TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CONFIG3H
MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX
354
Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
REGISTER 14-1: CCPxCON: STANDARD CCPx CONTROL REGISTER
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
— — DCxB<1:0> CCPxM<3:0>
bit 7 bit 0
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset
‘1’ = Bit is set ‘0’ = Bit is cleared
bit 7-6 Unused
bit 5-4 DCxB<1:0>: PWM Duty Cycle Least Significant bits
Capture mode:
Unused
Compare mode:
Unused
PWM mode:
These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
bit 3-0 CCPxM<3:0>: ECCPx Mode Select bits
0000 = Capture/Compare/PWM off (resets the module)
0001 = Reserved
0010 = Compare mode: toggle output on match
0011 = Reserved
0100 = Capture mode: every falling edge
0101 = Capture mode: every rising edge
0110 = Capture mode: every 4th rising edge
0111 = Capture mode: every 16th rising edge
1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set)
1001 = Compare mode: clear output on compare match (CCPx pin is cleared, CCPxIF is set)
1010 = Compare mode: generate software interrupt on compare match (CCPx pin is unaffected,
CCPxIF is set)
1011 = Compare mode: Special Event Trigger (CCPx pin is unaffected, CCPxIF is set)
TimerX (selected by CxTSEL bits) is reset
ADON is set, starting A/D conversion if A/D module is enabled
(1)
11xx =: PWM mode
Note 1: This feature is available on CCP5 only.