Datasheet

 2010 Microchip Technology Inc. Preliminary DS41412C-page 145
PIC18(L)F2X/4XK22
TABLE 10-9: REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2
— —153
ECCP1AS
CCP1ASE CCP1AS<2:0> P1SSAC<1:0> P1SSBD<1:0>
205
CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 201
ECCP2AS
CCP2ASE CCP2AS<2:0> P2SSAC<1:0> P2SSBD<1:0>
205
CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 201
CTMUCONH CTMUEN
— CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 329
LATC LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 155
PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 151
RCSTA1 SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 273
SLRCON
— — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 156
SSP1CON1
WCOL SSPOV SSPEN CKP SSPM<3:0> 256
T1CON TMR1CS<1:0>
T1CKPS<1:0> T1SOSCEN T1SYNC T1RD16 TMR1ON 170
T3CON TMR3CS<1:0>
T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 170
T3GCON TMR3GE
T3GPOL T3GTM T3GSPM T3GGO/DONE T3GVAL T3GSS 171
T5CON TMR5CS<1:0>
T5CKPS<1:0> T5OSCEN T5SYNC T5RD16 TMR5ON 170
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 154
TXSTA1 CSRC
TX9 TXEN SYNC SENDB BRGH TRMT TX9D 272
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.
Note 1: Available on PIC18(L)F4XK22 devices.
TABLE 10-10: CONFIGURATION REGISTERS ASSOCIATED WITH PORTC
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
CONFIG3H
MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 354
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTC.