Datasheet

 2010 Microchip Technology Inc. Preliminary DS41412C-page 141
PIC18(L)F2X/4XK22
RB6/KBI2/PGC RB6 01O DIG LATB<6> data output; not affected by analog input.
10 I ST PORTB<6> data input; disabled when analog input
enabled.
IOC2 10 I TTL Interrupt-on-change pin.
TX2
(3)
01O DIG EUSART 2 asynchronous transmit data output.
CK2
(3)
01O DIG EUSART 2 synchronous serial clock output.
10 I ST EUSART 2 synchronous serial clock input.
PGC xx I ST In-Circuit Debugger and ICSP
TM
programming clock input.
RB7/KBI3/PGD RB7 01O DIG LATB<7> data output; not affected by analog input.
10 I ST PORTB<7> data input; disabled when analog input
enabled.
IOC3 10 I TTL Interrupt-on-change pin.
RX2
(2), (3)
10 I ST EUSART 2 asynchronous receive data input.
DT2
(2), (3)
01O DIG EUSART 2 synchronous serial data output.
10 I ST EUSART 2 synchronous serial data input.
PGD xxO DIG In-Circuit Debugger and ICSP
TM
programming data output.
xx I ST In-Circuit Debugger and ICSP
TM
programming data input.
TABLE 10-5: PORTB I/O SUMMARY (CONTINUED)
Pin Function
TRIS
Setting
ANSEL
Setting
Pin
Type
Buffer
Type
Description
Legend: AN = Analog input or output; TTL = TTL compatible input; HV = High Voltage; OD = Open Drain; XTAL = Crystal; CMOS =
CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I
2
C
TM
= Schmitt Trigger input with I
2
C.
Note 1: Default pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are set.
2: Alternate pin assignment for P2B, T3CKI, CCP3 and CCP2 when Configuration bits PB2MX, T3CMX, CCP3MX and
CCP2MX are clear.
3: Function on PORTD and PORTE for PIC18(L)F4XK22 devices.
TABLE 10-6: REGISTERS ASSOCIATED WITH PORTB
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELB
— — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 153
ECCP2AS
CCP2ASE CCP2AS<2:0> P2SSAC<1:0> P2SSBD<1:0>
205
CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 201
ECCP3AS
CCP3ASE CCP3AS<2:0> P3SSAC<1:0> P3SSBD<1:0>
205
CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 201
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115
INTCON2 R
BPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP —RBIP116
INTCON3 INT2IP INT1IP
— INT2IE INT1IE — INT2IF INT1IF 117
IOCB IOCB7 IOCB6 IOCB5 IOCB4
— — — —156
LATB LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 155
PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 151
SLRCON
— — — SLRE
(1)
SLRD
(1)
SLRC SLRB SLRA 156
T1GCON TMR1GE
T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0> 171
T3CON TMR3CS<1:0>
T3CKPS<1:0> T3SOSCEN T3SYNC T3RD16 TMR3ON 170
T5GCON TMR5GE
T5GPOL T5GTM T5GSPM T5GGO_DONE T5GVAL T5GSS 171
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 154
WPUB WPUB7 WPUB6 WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 155
Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB.
Note 1: Available on PIC18(L)F4XK22 devices.