PIC18(L)F2X/4XK22 Data Sheet 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology 2010 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC18(L)F2X/4XK22 28/40/44-Pin, Low-Power, High-Performance Microcontrollers with nanoWatt XLP Technology High-Performance RISC CPU: Extreme Low-Power Management with nanoWatt XLP: • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • Up to 1024 Bytes Data EEPROM • Up to 64 Kbytes Linear Program Memory Addressing • Up to 3896 Bytes Linear Data Memory Addressing • Up to 16 MIPS Operation • 16-bit Wide Instructions, 8-bit Wide Data Path • Priority Le
PIC18(L)F2X/4XK22 • Two Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) modules: - Supports RS-485, RS-232 and LIN - RS-232 operation using internal oscillator - Auto-Wake-up on Break - Auto-Baud Detect SRAM (Bytes) EEPROM (Bytes) I/O(1) 10-bit A/D Channels(2) CCP ECCP (Full-Bridge) ECCP (Half-Bridge) SPI I2C™ EUSART Comparator CTMU BOR/LVD SR Latch 8-bit Timer 16-bit Timer MSSP # Single-Word Instructions Data Memory Flash (Bytes) Program Memory PIC18(L)F23K22
PIC18(L)F2X/4XK22 Pin Diagrams 28-pin PDIP, SOIC, SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RC7 RC6 RC5 RC4 RA1 RA0 MCLR/VPP/RE3 RB7 RB6 RB5 RB4 28-pin QFN, UQFN(1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC18(L)F2XK22 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 VSS RA7 RA6 RC0 RC1 RC2 RC3 28 27 26 25 24 23 22 1 2 3 4 PIC18(L)F2XK22 5 6 7 8 9 10 11 12 13 14 21 20 19 18 17 16 15 RB3 RB2 RB1 RB0 VDD VSS RC7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RA2 RA3 RA4 RA5/ VSS RA7 RA6 No
PIC18(L)F2X/4XK22 Pin Diagrams 40-pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 PIC18(L)F4XK22 MCLR/VPP/RE3 RA0 RA1 RA2 RA3 RA4 RA5 RE0 RE1 RE2 VDD VSS RA7 RA6 RC0 RC1 RC2 RC3 RD0 RD1 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 VDD VSS RD7 RD6 RD5 RD4 RC7 RC6 RC5 RC4 RD3 RD2 40 39 38 37 36 35 34 33 32 31 RC6 RC5 RC4 RD3 RD2 RD1 RD0 RC3 RC2 RC1 40-pin UQFN 1 2 3 4 5 PIC18(L)F4XK22 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RC0 RA6 RA7 VSS
PIC18(L)F2X/4XK22 Pin Diagrams (Cont.
PIC18(L)F2X/4XK22 C2IN+ AN3 5 2 RA3 6 3 RA4 AN4 Basic AN2 Pull-up RA2 Interrupts 1 Timers C12IN1- 4 MSSP C12IN0- AN1 EUSART AN0 RA1 (E)CCP RA0 28 Reference Comparator 27 3 SR Latch Analog 2 CTMU I/O PIC18(L)F2XK22 PIN SUMMARY 28-QFN, UQFN 28-SSOP, SOIC 28-SPDIP TABLE 1: VREF-/ DACOUT C1IN+ VREF+ C1OUT SRQ C2OUT SRNQ CCP5 T0CKI 7 4 RA5 10 7 RA6 OSC2/ CLKO 9 6 RA7 OSC1/ CLKI 21 18 RB0 AN12 22 19 RB1 AN10 23 20 RB2 AN8 24 21 RB3 AN9 SR
PIC18(L)F2X/4XK22 21 21 RA2 AN2 C2IN+ AN3 Basic 19 Pull-up C12IN1- 4 Interrupts C12IN0- AN1 Timers AN0 RA1 MSSP Comparator RA0 20 EUSART Analog 19 20 (E)CCP I/O 19 18 Reference 44-QFN 17 3 SR Latch 44-TQFP 2 CTMU 40-UQFN PIC18(L)F4XK22 PIN SUMMARY 40-PDIP TABLE 2: VREFDACOUT 5 20 22 22 RA3 6 21 23 23 RA4 7 22 24 24 RA5 14 29 31 33 RA6 OSC2/ CLKO 13 28 30 32 RA7 OSC1/ CLKI AN4 C1IN+ VREF+ C1OUT SRQ C2OUT SRN Q T0CKI HLVDIN SRI SS1
PIC18(L)F2X/4XK22 Interrupts P3B 10 25 27 27 RE2 AN7 CCP5 1 16 18 18 RE3 11 32 7, 26 7 28 7,8 28, 29 VDD 12 31 6, 27 6 29 6 30, 31 VSS — — 12, 13 33, 34 13 Note 1: 2: 3: 4: Basic AN6 Pull-up RE1 Timers 26 MSSP 26 EUSART Analog 24 (E)CCP I/O Reference 44-QFN SR Latch 44-TQFP 9 CTMU 40-UQFN Comparator PIC18(L)F4XK22 PIN SUMMARY (CONTINUED) 40-PDIP TABLE 2: Y MCLR/ VPP NC CCP2 multiplexed in fuses. T3CKI multiplexed in fuses.
PIC18(L)F2X/4XK22 Table of Contents 1.0 Device Overview ....................................................................................................................................................................... 13 2.0 Oscillator Module (With Fail-Safe Clock Monitor)...................................................................................................................... 27 3.0 Power-Managed Modes .......................................................................................
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PIC18(L)F2X/4XK22 1.0 DEVICE OVERVIEW 1.1.
PIC18(L)F2X/4XK22 1.2 Other Special Features 1.3 • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control.
A, B, C, E(1) A, B, C, E(1) Data EEPROM Memory (Bytes) 2010 Microchip Technology Inc. 1 2 internal 17 input Enhanced CCP Modules (ECCP) - Full Bridge 10-bit Analog-to-Digital Module (ADC) Preliminary Yes Yes Yes Programmable High/Low-Voltage Detect (HLVD) Programmable Brown-out Reset (BOR) Note 1: PORTE contains the single RE3 read-only bit.
PIC18(L)F2X/4XK22 FIGURE 1-1: PIC18(L)F2X/4XK22 FAMILY BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic Data Memory PCLATU PCLATH 21 PORTA Address Latch 20 PCU PCH PCL Program Counter RA0:RA7 12 Data Address<12> 31-Level Stack 4 BSR Address Latch Program Memory (8/16/32/64 Kbytes) STKPTR 12 FSR0 FSR1 FSR2 Data Latch 8 PORTB 12 RB0:RB7 inc/dec logic Table Latch Instruction Bus <16> 4 Access Bank Address Decode ROM Latch PORTC RC0:RC7 IR Instruction Decod
PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS Pin Number PDIP, SOIC QFN, UQFN 2 27 3 28 4 1 5 2 6 3 7 4 10 7 Legend: Note 1: 2: Pin Type Pin Name Buffer Type Description RA0/C12IN0-/AN0 RA0 I/O TTL C12IN0- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN0 I Analog Analog input 0. RA1/C12IN1-/AN1 RA1 I/O TTL C12IN1- I Analog Comparators C1 and C2 inverting input. Digital I/O. AN1 I Analog Analog input 1.
PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN 9 6 21 18 22 19 23 20 24 21 Legend: Note 1: 2: Pin Type Pin Name Buffer Type Description RA7/CLKI/OSC1 RA7 I/O TTL CLKI I CMOS External clock source input. Always associated with pin function OSC1. Digital I/O. OSC1 I ST Oscillator crystal input or external clock source input ST buffer when configured in RC mode; CMOS otherwise.
PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN 25 22 26 23 Pin Name 24 28 25 11 8 12 9 Note 1: 2: Description RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. P1D O CMOS T5G I ST AN11 I Analog Enhanced CCP1 PWM output. Timer5 external clock gate input. Analog input 11. RB5/IOC1/P2B/P3A/CCP3/T3CKI/T1G/AN13 I/O TTL Digital I/O. Interrupt-on-change pin.
PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP, SOIC QFN, UQFN Pin Name 13 10 RC2/CTPLS/P1A/CCP1/T5CKI/AN14 14 11 15 12 16 13 17 14 15 1 26 Legend: Note 1: 2: Buffer Type Description RC2 I/O TTL CTPLS O — CTMU pulse generator output. P1A O CMOS Enhanced CCP1 PWM output. Digital I/O. CCP1 I/O ST Capture 1 input/Compare 1 output/PWM 1 output. T5CKI I ST Timer5 clock input. AN14 I Analog Analog input 14.
PIC18(L)F2X/4XK22 TABLE 1-2: PIC18(L)F2XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number QFN, UQFN Pin Name Pin Type Buffer Type 20 17 VDD P — Positive supply for logic and I/O pins. 8, 19 5, 16 VSS P — Ground reference for logic and I/O pins. PDIP, SOIC Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output; ST = Schmitt Trigger input with CMOS levels; I = Input; O = Output; P = Power.
PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 7 24 24 22 14 13 33 34 35 36 31 30 32 8 9 9 10 10 11 Legend: Note 33 11 12 29 28 8 9 10 11 Pin Type Pin Name Buffer Type Description RA5/C2OUT/SRNQ/SS1/HLVDIN/AN4 RA5 I/O TTL Digital I/O. C2OUT O SRNQ O TTL SR Latch Q output. SS1 I TTL SPI slave select input (MSSP1). HLVDIN I Analog High/Low-Voltage Detect input. AN4 I Analog Analog input 4.
PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 37 14 14 12 38 15 15 13 Pin Type Buffer Type RB4 I/O TTL Digital I/O. IOC0 I TTL Interrupt-on-change pin. T5G I ST Timer5 external clock gate input. AN11 I Pin Name RB4/IOC0/T5G/AN11 40 15 16 16 17 32 35 16 17 34 35 14 15 30 31 RB5 I/O TTL Digital I/O. IOC1 I TTL Interrupt-on-change pin.
PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 18 37 37 33 23 24 25 26 19 20 42 43 44 43 44 1 1 38 39 Legend: Note 42 38 39 38 39 40 1 34 35 Pin Type Buffer Type RC3 I/O TTL Digital I/O. SCK1 I/O ST Synchronous serial clock input/output for SPI mode (MSSP2). SCL1 I/O ST Synchronous serial clock input/output for I2C™ mode (MSSP2).
PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 21 40 40 36 22 27 28 29 30 8 9 41 2 Note 2 3 3 4 4 5 5 25 26 Legend: 41 25 26 37 2 3 4 5 23 24 Pin Type Buffer Type RD2 I/O TTL P2B(1) O CMOS Enhanced CCP2 PWM output. AN22 I Analog Analog input 22. Pin Name Description RD2/P2B/AN22 Digital I/O RD3/P2C/SS2/AN23 RD3 I/O P2C O SS2 I AN23 I TTL Digital I/O. CMOS Enhanced CCP2 PWM output.
PIC18(L)F2X/4XK22 TABLE 1-3: PIC18(L)F4XK22 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number PDIP TQFP QFN UQFN 10 27 27 25 1 18 18 16 Pin Type Buffer Type RE2 I/O TTL Digital I/O. CCP5 I/O ST Capture 5 input/Compare 5 output/PWM 5 output AN7 I Pin Name Description RE2/CCP5/AN7 Analog Analog input 7. RE3/VPP/MCLR RE3 I ST Digital input. VPP P MCLR I ST Active-low Master Clear (device Reset) input. Programming voltage input.
PIC18(L)F2X/4XK22 2.0 OSCILLATOR MODULE (WITH FAIL-SAFE CLOCK MONITOR) 2.1 Overview The HFINTOSC, MFINTOSC and LFINTOSC are factory calibrated high, medium and low-frequency oscillators, respectively, which are used as the internal clock sources. The oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption.
PIC18(L)F2X/4XK22 FIGURE 2-1: SIMPLIFIED OSCILLATOR SYSTEM BLOCK DIAGRAM Secondary Oscillator(1) SOSCO Secondary Oscillator (SOSC) SOSCI Low-Power Mode Event Switch (SCS<1:0>) SOSCOUT 2 Primary Clock Module Secondary Oscillator PRICLKEN PRISD PLL Select (3) (4) OSC2 OSC1 FOSC<3:0>(5) Primary Oscillator(2) ( OSC) Primary Oscillator INTOSC 0 4xPLL 0 Primary Clock 00 1 1 INTOSC Clock Switch MUX EN 01 1x Internal Oscillator IRCF<2:0> MFIOSEL INTSRC 3 3 INTOSC Divide Circuit HF-1
PIC18(L)F2X/4XK22 2.2 Oscillator Control 2.2.3 The OSCCON, OSCCON2 and OSCTUNE registers (Register 2-1 to Register 2-3) control several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. • • • • • • Main System Clock Selection (SCS) Primary Oscillator Circuit Shutdown (PRISD) Secondary Oscillator Enable (SOSCGO) Primary Clock Frequency 4x multiplier (PLLEN) Internal Frequency selection bits (IRCF, INTSRC) Clock Status bits (OSTS, HFIOFS, MFIOFS, LFIOFS.
PIC18(L)F2X/4XK22 FIGURE 2-2: INTERNAL OSCILLATOR MUX BLOCK DIAGRAM FIGURE 2-3: FOSC<3:0> = 100x PLLCFG IRCF<2:0> MFIOSEL INTSRC PLL 3 HF-16 MHZ HF-8 MHZ HF-4 MHZ HF-2 MHZ HF-1 MHZ PLLEN Select 111 110 101 100 011 MF-500 KHZ 1 HF-500 KHZ 500 kHZ 010 250 kHZ 001 0 MF-250 KHZ 1 HF-250 KHZ INTOSC 0 HF-31.25 KHZ 11 MF-31.25 KHZ 10 LF-31.25 KHZ 0X TABLE 2-1: PLL SELECT BLOCK DIAGRAM 31.
PIC18(L)F2X/4XK22 FIGURE 2-4: SECONDARY OSCILLATOR AND EXTERNAL CLOCK INPUTS SOSCGO T1SOSCEN T3SOSCEN T5SOSCEN SOSCEN To Clock Switch Module SOSCI EN SOSCOUT Secondary Oscillator SOSCO T1CKI T3G T3CKI 1 T1CLK_EXT_SRC SOSCEN 0 T1SOSCEN SOSCEN T3G SOSCEN 1 T3CLK_EXT_SRC 0 0 1 T3CKI T1G T3SOSCEN T3CMX T1G 1 T5CLK_EXT_SRC 0 T5CKI T5SOSCEN T5G 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 REGISTER 2-1: R/W-0 OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 IDLEN R/W-1 R/W-1 IRCF<2:0> R-q R-0 OSTS(1) HFIOFS R/W-0 R/W-0 SCS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 IRCF<2:0>
PIC18(L)F2X/4XK22 REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 R-0/0 R-0/q U-0 R/W-0/0 R/W-0/u R/W-1/1 R-x/u R-0/0 PLLRDY SOSCRUN — MFIOSEL SOSCGO(1) PRISD MFIOFS LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown q = depends on condition -n/n = Value at POR and BOR/Value at all other Resets bit 7 PLLRDY: PLL Run Status bit 1 = System clock comes from 4xPLL 0 = System clo
PIC18(L)F2X/4XK22 2.3 Clock Source Modes Clock Source modes can be classified as external or internal. 2.4 External Clock Modes 2.4.1 OSCILLATOR START-UP TIMER (OST) • External Clock modes rely on external circuitry for the clock source. Examples are: Clock modules (EC mode), quartz crystal resonators or ceramic resonators (LP, XT and HS modes) and ResistorCapacitor (RC mode) circuits. • Internal clock sources are contained internally within the Oscillator block.
PIC18(L)F2X/4XK22 2.4.3 LP, XT, HS MODES The LP, XT and HS modes support the use of quartz crystal resonators or ceramic resonators connected to OSC1 and OSC2 (Figure 2-6). The mode selects a low, medium or high gain setting of the internal inverteramplifier to support various resonator types and speed. Note 1: Quartz crystal characteristics vary according to type, package and manufacturer. The user should consult the manufacturer data sheets for specifications and recommended application.
PIC18(L)F2X/4XK22 2.4.4 2.5 EXTERNAL RC MODES The external Resistor-Capacitor (RC) modes support the use of an external RC circuit. This allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. There are two modes: RC and RCIO. 2.4.4.1 FIGURE 2-8: 1.
PIC18(L)F2X/4XK22 2.5.1.1 OSCTUNE Register The HFINTOSC/MFINTOSC oscillator circuits are factory calibrated but can be adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register (Register 2-3). The default value of the TUN<5:0> is ‘000000’. The value is a 6-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC/MFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift.
PIC18(L)F2X/4XK22 2.5.2 LFINTOSC 2.5.4.1 The Low-Frequency Internal Oscillator (LFINTOSC) is a 31.25 kHz internal clock source. The LFINTOSC is not tunable, but is designed to be stable across temperature and voltage. See Section 27.0 “Electrical Characteristics” for the LFINTOSC accuracy specifications. The output of the LFINTOSC can be a clock source to the primary clock or the INTOSC clock (see Figure 2-1).
PIC18(L)F2X/4XK22 2.6 PLL Frequency Multiplier 2.6.2 A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower frequency oscillator circuit or to clock the device up to its highest rated frequency from the crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from an internal oscillator. 2.6.
PIC18(L)F2X/4XK22 2.7 Effects of Power-Managed Modes on the Various Clock Sources For more information about the modes discussed in this section see Section 3.0 “Power-Managed Modes”. A quick reference list is also available in Table 3-1. When PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. The OSC1 pin (and OSC2 pin, if used by the oscillator) will stop oscillating.
PIC18(L)F2X/4XK22 TABLE 2-3: OSC1 AND OSC2 PIN STATES IN SLEEP MODE OSC Mode OSC1 Pin OSC2 Pin RC, INTOSC with CLKOUT Floating, external resistor should pull high At logic low (clock/4 output) RC with IO Floating, external resistor should pull high Configured as PORTA, bit 6 INTOSC with IO Configured as PORTA, bit 7 Configured as PORTA, bit 6 EC with IO Floating, pulled by external clock Configured as PORTA, bit 6 EC with CLKOUT Floating, pulled by external clock At logic low (clock/4 outp
PIC18(L)F2X/4XK22 2.9.3 2.10 CLOCK SWITCH TIMING When switching between one oscillator and another, the new oscillator may not be operating which saves power (see Figure 2-9). If this is the case, there is a delay after the SCS<1:0> bits of the OSCCON register are modified before the frequency change takes place. The OSTS and IOFS bits of the OSCCON register will reflect the current active status of the external and HFINTOSC oscillators. The timing of a frequency selection is as follows: 1. 2. 3. 4. 5.
PIC18(L)F2X/4XK22 2.10.2 1. 2. 3. 4. 5. 6. TWO-SPEED START-UP SEQUENCE 2.10.3 Wake-up from Power-on Reset or Sleep. Instructions begin executing by the internal oscillator at the frequency set in the IRCF<2:0> bits of the OSCCON register. OST enabled to count 1024 external clock cycles. OST timed out. External clock is ready. OSTS is set.
PIC18(L)F2X/4XK22 2.11 Fail-Safe Clock Monitor 2.11.3 The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC, RC and RCIO).
PIC18(L)F2X/4XK22 FIGURE 2-11: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: TABLE 2-4: Name INTCON IPR2 OSCCON Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 46 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 3.0 POWER-MANAGED MODES 3.1.1 The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18(L)F2X/4XK22 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18(L)F2X/4XK22 3.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND The power-managed mode that is invoked with the SLEEP instruction is determined by the value of the IDLEN bit at the time the instruction is executed. If IDLEN = 0, when SLEEP is executed, the device enters the sleep mode and all clocks stop and minimum power is consumed. If IDLEN = 1, when SLEEP is executed, the device enters the IDLE mode and the system clock continues to supply a clock to the peripherals but is disconnected from the CPU.
PIC18(L)F2X/4XK22 On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC multiplexer while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 3-3). When the clock switch is complete, the HFIOFS or MFIOFS bit is cleared, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch.
PIC18(L)F2X/4XK22 FIGURE 3-3: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 Q2 Q3 Q4 Q2 Q3 Q4 Q1 Q2 Q3 Q1 INTOSC Multiplexer OSC1 TOST(1) TPLL(1) 1 PLL Clock Output 2 n-1 n Clock Transition(2) CPU Clock Peripheral Clock Program Counter PC + 2 PC SCS<1:0> bits Changed PC + 4 OSTS bit Set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 2: Clock transition typically occurs within 2-4 TOSC.
PIC18(L)F2X/4XK22 3.3 Sleep Mode 3.4 The Power-Managed Sleep mode in the PIC18(L)F2X/ 4XK22 devices is identical to the legacy Sleep mode offered in all other PIC® microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 3-4) and all clock source status bits are cleared.
PIC18(L)F2X/4XK22 FIGURE 3-5: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 OSC1 TOST(1) PLL Clock Output TPLL(1) CPU Clock Peripheral Clock Program Counter PC Wake Event PC + 2 PC + 4 PC + 6 OSTS bit set Note1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. 3.4.1 3.4.2 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock.
PIC18(L)F2X/4XK22 FIGURE 3-7: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 TCSD CPU Clock Peripheral Clock Program Counter PC Wake Event 3.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction.
PIC18(L)F2X/4XK22 3.5 Exiting Idle and Sleep Modes 3.5.2 An exit from Sleep mode or any of the Idle modes is triggered by any one of the following: • an interrupt • a Reset • a Watchdog Time-out This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes (see Section 3.2 “Run Modes”, Section 3.3 “Sleep Mode” and Section 3.4 “Idle Modes”). 3.5.
PIC18(L)F2X/4XK22 TABLE 3-3: EXIT DELAY ON WAKE-UP BY RESET FROM SLEEP MODE OR ANY IDLE MODE (BY CLOCK SOURCES) Clock Source before Wake-up Clock Source after Wake-up Exit Delay Clock Ready Status Bit (OSCCON) LP, XT, HS Primary Device Clock (PRI_IDLE mode) HSPLL EC, RC TCSD(1) HFINTOSC(2) T1OSC or LFINTOSC(1) HFINTOSC(2) None (Sleep mode) 2: 3: 4: IOSF LP, XT, HS TOST(3) HSPLL TOST + tPLL(3) EC, RC TCSD(1) HFINTOSC(1) TIOBST(4) LP, XT, HS TOST(4) HSPLL TOST + tPLL(3) EC, RC TCSD
PIC18(L)F2X/4XK22 3.6 Selective Peripheral Module Control Idle mode allows users to substantially reduce power consumption by stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what IDLE mode does not provide: the allocation of power resources to the CPU processing with minimal power consumption from the peripherals.
PIC18(L)F2X/4XK22 REGISTER 3-2: PMD1: PERIPHERAL MODULE DISABLE REGISTER 1 R/W-0 R/W-0 MSSP2MD MSSP1MD U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — CCP5MD CCP4MD CCP3MD CCP2MD CCP1MD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 MSSP2MD: MSSP2 Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw digital powe
PIC18(L)F2X/4XK22 REGISTER 3-3: PMD2: PERIPHERAL MODULE DISABLE REGISTER 2 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — CTMUMD CMP2MD CMP1MD ADCMD bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3 CTMUMD: CTMU Peripheral Module Disable Control bit 1 = Module is disabled, Clock Source is disconnected, module does not draw d
PIC18(L)F2X/4XK22 4.0 RESET The PIC18(L)F2X/4XK22 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset 4.1 RCON Register Device Reset events are tracked through the RCON register (Register 4-1).
PIC18(L)F2X/4XK22 REGISTER 4-1: R/W-0/0 IPEN RCON: RESET CONTROL REGISTER R/W-q/u SBOREN (1) U-0 R/W-1/q — RI R-1/q R-1/q TO R/W-q/u (2) PD POR bit 7 R/W-0/q BOR bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n/n = Value at POR and BOR/Value at all other Resets x = Bit is unknown u = unchanged q = depends on condition bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disa
PIC18(L)F2X/4XK22 4.2 Master Clear (MCLR) FIGURE 4-2: The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. An internal weak pull-up is enabled when the pin is configured as the MCLR input. In PIC18(L)F2X/4XK22 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input.
PIC18(L)F2X/4XK22 4.4 Brown-out Reset (BOR) 4.4.2 PIC18(L)F2X/4XK22 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 4-1. The BOR threshold is set by the BORV<1:0> bits.
PIC18(L)F2X/4XK22 TABLE 4-1: BOR CONFIGURATIONS BOR Configuration BOREN1 BOREN0 Status of SBOREN (RCON<6>) 0 0 Unavailable 0 1 Available 1 0 Unavailable BOR enabled by hardware in Run and Idle modes, disabled during Sleep mode. 1 1 Unavailable BOR enabled by hardware; must be disabled by reprogramming the Configuration bits. 4.5 BOR Operation BOR disabled; must be enabled by reprogramming the Configuration bits. BOR enabled by software; operation controlled by SBOREN.
PIC18(L)F2X/4XK22 TABLE 4-2: TIME-OUT IN VARIOUS SITUATIONS Oscillator Configuration HSPLL Power-up(2) and Brown-out PWRTEN = 1 Exit from Power-Managed Mode 1024 TOSC + 2 ms(2) 1024 TOSC + 2 ms(2) PWRTEN = 0 66 ms (1) + 1024 TOSC + 2 ms(2) 66 ms(1) + 1024 TOSC HS, XT, LP 1024 TOSC 1024 TOSC EC, ECIO (1) 66 ms — — RC, RCIO 66 ms(1) — — ms(1) — — INTIO1, INTIO2 66 Note 1: 66 ms (65.5 ms) is the nominal Power-up Timer (PWRT) delay.
PIC18(L)F2X/4XK22 FIGURE 4-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 FIGURE 4-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. DS41412C-page 66 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 4.6 Reset State of Registers Table 5-2 describes the Reset states for all of the Special Function Registers. The table identifies differences between Power-On Reset (POR)/BrownOut Reset (BOR) and all other Resets, (i.e., Master Clear, WDT Resets, STKFUL, STKUNF, etc.). Additionally, the table identifies register bits that are changed when the device receives a wake-up from WDT or other interrupts. Some registers are unaffected by a Reset.
PIC18(L)F2X/4XK22 TABLE 4-5: CONFIGURATION REGISTERS ASSOCIATED WITH RESETS Name Bit 7 Bit 6 Bit 5 CONFIG2L — — — CONFIG2H — — Bit 4 Bit 3 BORV<1:0> Bit 2 BOREN<1:0> WDPS<3:0> CONFIG3H MCLRE — P2BMX T3CMX CONFIG4L DEBUG XINST — — Bit 0 Register on Page PWRTEN 352 WDTEN<1:0> HFOFST CCP3MX — Bit 1 LVP 353 PBADEN CCP2MX 354 — STRVEN 355 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Resets.
PIC18(L)F2X/4XK22 5.0 MEMORY ORGANIZATION 5.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM As Harvard architecture devices, the data and program memories use separate buses; this allows for concurrent access of the two memory spaces. The data EEPROM, for practical purposes, can be regarded as a peripheral device, since it is addressed and accessed through a set of control registers.
PIC18(L)F2X/4XK22 FIGURE 5-1: PROGRAM MEMORY MAP AND STACK FOR PIC18(L)F2X/4XK22 DEVICES PC<20:0> 21 CALL,RCALL,RETURN RETFIE,RETLW Stack Level 1 Stack Level 31 2000h 0000h High Priority Interrupt Vector 0008h Low Priority Interrupt Vector 0018h On-Chip Program Memory 3FFFh 4000h PIC18(L)F23K22 PIC18(L)F43K22 On-Chip Program Memory User Memory Space On-Chip Program Memory 1FFFh Reset Vector On-Chip Program Memory PIC18(L)F24K22 PIC18(L)F44K22 7FFFh 8000h PIC18(L)F25K22 PIC18(L)F45K22
PIC18(L)F2X/4XK22 A CALL type instruction causes a push onto the stack; the Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack; the contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to ‘00000’ after all Resets.
PIC18(L)F2X/4XK22 5.1.2.3 PUSH and POP Instructions The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. Since the Top-of-Stack is readable and writable, the ability to push values onto the stack and pull values off the stack without disturbing normal program execution is a desirable feature.
PIC18(L)F2X/4XK22 EXAMPLE 5-1: FAST REGISTER STACK CODE EXAMPLE CALL SUB1, FAST ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK RETURN, FAST SUB1 5.1.4 ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK 5.1.4.2 Table Reads and Table Writes A better method of storing data in program memory allows two bytes of data to be stored in each instruction location. Look-up table data may be stored two bytes per program word by using table reads and writes.
PIC18(L)F2X/4XK22 5.2 PIC18 Instruction Cycle 5.2.1 5.2.2 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18(L)F2X/4XK22 5.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 5.1.1 “Program Counter”).
PIC18(L)F2X/4XK22 5.3 Note: Data Memory Organization 5.3.1 The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18(L)F2X/4XK22 FIGURE 5-5: DATA MEMORY MAP FOR PIC18(L)F23K22 AND PIC18(L)F43K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 FFh 00h 1FFh 200h FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h 7FFh 800h FFh 00h Unused Read 0
PIC18(L)F2X/4XK22 FIGURE 5-6: DATA MEMORY MAP FOR PIC18(L)F24K22 AND PIC18(L)F44K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 GPR FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h Unused Read 00h AFFh B00h FFh 00h BFFh C00h
PIC18(L)F2X/4XK22 FIGURE 5-7: DATA MEMORY MAP FOR PIC18(L)F25K22 AND PIC18(L)F45K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 GPR FFh 00h 2FFh 300h GPR 4FFh 500h FFh 00h GPR FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h 7FFh 800h FFh 00h 8FFh 900h FFh 00h Unused Rea
PIC18(L)F2X/4XK22 FIGURE 5-8: DATA MEMORY MAP FOR PIC18(L)F26K22 AND PIC18(L)F46K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 = 1111 When ‘a’ = 0: Data Memory Map 00h Access RAM FFh 00h GPR Bank 0 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 Bank 10 Bank 11 Bank 12 GPR FFh 00h 2FFh 300h When ‘a’ = 1: The BSR specifies the Bank used by the instruction.
PIC18(L)F2X/4XK22 FIGURE 5-9: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 7 0 0 0 0 0 0 0 Bank Select(2) 1 1 000h Data Memory 00h Bank 0 100h Bank 1 200h 300h Bank 2 FFh 00h From Opcode(2) 7 1 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18(L)F2X/4XK22 5.3.2 ACCESS BANK 5.3.3 While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead.
PIC18(L)F2X/4XK22 TABLE 5-1: Address SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F2X/4XK22 DEVICES Name Address Name Address Name Address Name Address (2) F5Fh Name FFFh TOSU FD7h TMR0H FAFh SPBRG1 F87h — FFEh TOSH FD6h TMR0L FAEh RCREG1 F86h —(2) F5Eh CCPR3L FFDh TOSL FD5h T0CON FADh TXREG1 F85h —(2) F5Dh CCP3CON FFCh STKPTR FD4h —(2) FACh TXSTA1 F84h PORTE F5Ch PWM3CON F5Bh ECCP3AS F5Ah PSTR3CON CCPR3H FFBh PCLATU FD3h OSCCON FABh RCSTA1 F83h POR
PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Name Bit 7 Bit 6 Bit 5 — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FFFh TOSU FFEh TOSH Top-of-Stack, High Byte (TOS<15:8>) 0000 0000 FFDh TOSL Top-of-Stack, Low Byte (TOS<7:0>) 0000 0000 FFCh STKPTR STKFUL STKUNF — STKPTR<4:0> 00-0 0000 FFBh PCLATU — — — Holding Register for PC<20:16> ---0 0000 FFAh PCLATH Holding Register for PC<15:8> FF9h PCL Holding Register for PC<7:0> FF8h TBLPT
PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — — — — — IPEN SBOREN — RI TO Bit 2 FD1h WDTCON FD0h RCON FCFh TMR1H Timer1 Register, High Byte FCEh TMR1L Timer1 Register, Low Byte FCDh T1CON FCCh T1GCON TMR1GE T1GPOL T1GTM FCBh SSP1CON3 ACKTIM PCIE SCIE FCAh SSP1MSK SSP1 MASK Register bits FC9h SSP1BUF SSP1 Receive Buffer/Transmit Register FC8h SSP1ADD FC7h SSP1STAT SMP CKE D/A
PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR FA2h IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 1111 1111 FA1h PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 0000 0000 FA0h PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 0000 0000 F9Fh IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP -111 1111 F9Eh PIR1 — ADIF
PIC18(L)F2X/4XK22 TABLE 5-2: Address REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 F68h CCPR2H Capture/Compare/PWM Register 2, High Byte F67h CCPR2L Capture/Compare/PWM Register 2, Low Byte F66h CCP2CON F65h PWM2CON P2RSEN F64h ECCP2AS CCP2ASE F63h PSTR2CON F62h F61h P2M<1:0> DC2B<1:0> Bit 1 Bit 0 xxxx xxxx xxxx xxxx CCP2M<3:0> 0000 0000 P2DC<6:0> CCP2AS<2:0> Value on POR, BOR 0000 0000 P2SSAC<1:0> P2SSBD<1:0> 0000 0000 —
PIC18(L)F2X/4XK22 TABLE 5-2: Address Name REGISTER FILE SUMMARY FOR PIC18(L)F2X/4XK22 DEVICES Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR F3Ah ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 1111 11-- F39h ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 --11 1111 F38h ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 --1- 1111 Legend: Note 1: 2: 3: 4: x = unknown, u = unchanged, — = unimplemented, q = value depends on condition PIC18(L)F4XK22 devices
PIC18(L)F2X/4XK22 5.3.5 STATUS REGISTER The STATUS register, shown in Register 5-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
PIC18(L)F2X/4XK22 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.5 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18(L)F2X/4XK22 5.4.3.1 FSR Registers and the INDF Operand 5.4.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore, the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18(L)F2X/4XK22 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space.
PIC18(L)F2X/4XK22 FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
PIC18(L)F2X/4XK22 5.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space.
PIC18(L)F2X/4XK22 6.0 FLASH PROGRAM MEMORY 6.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time. A write to program memory is executed on blocks of 64 bytes at a time.
PIC18(L)F2X/4XK22 FIGURE 6-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written.
PIC18(L)F2X/4XK22 REGISTER 6-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memo
PIC18(L)F2X/4XK22 6.2.2 TABLAT – TABLE LATCH REGISTER When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register. The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.
PIC18(L)F2X/4XK22 6.3 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 6-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18(L)F2X/4XK22 6.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP™ control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored.
PIC18(L)F2X/4XK22 6.5 Writing to Flash Program Memory The programming block size is 64 bytes. Word or byte programming is not supported. The long write is necessary for programming the internal Flash. Instruction execution is halted during a long write cycle. The long write will be terminated by the internal programming timer. Table writes are used internally to load the holding registers needed to program the Flash memory.
PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; poi
PIC18(L)F2X/4XK22 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 6.5.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 104 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 7.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18(L)F2X/4XK22 REGISTER 7-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memo
PIC18(L)F2X/4XK22 7.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation).
PIC18(L)F2X/4XK22 7.6 Operation During Code-Protect Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 24.0 “Special Features of the CPU” for additional information. 7.
PIC18(L)F2X/4XK22 TABLE 7-1: Name REGISTERS ASSOCIATED WITH DATA EEPROM MEMORY Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL EEADR EEADR7 EEADR6 — — (1) EEADRH Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 — — — EEDATA EEPROM Data Register EECON2 EEPROM Control Register 2 (not a physical register) — EEADR9 EEADR8 — — — — EECON1 EEPGD CFGS — FREE WRERR WREN WR RD 106 IPR2 OSCFIP
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 110 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 8.0 8 x 8 HARDWARE MULTIPLIER 8.1 Introduction All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle.
PIC18(L)F2X/4XK22 Example 8-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>).
PIC18(L)F2X/4XK22 9.0 INTERRUPTS 9.2 The PIC18(L)F2X/4XK22 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high or low priority level (INT0 does not have a priority bit, it is always a high priority). The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress.
PIC18(L)F2X/4XK22 instructions. Individual interrupt flag bits are set, regardless of the status of their corresponding enable bits or the Global Interrupt Enable bit. Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
PIC18(L)F2X/4XK22 9.4 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. REGISTER 9-1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18(L)F2X/4XK22 REGISTER 9-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RBPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RBIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled provided that the pin is an input and the corresponding W
PIC18(L)F2X/4XK22 REGISTER 9-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 5
PIC18(L)F2X/4XK22 9.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Request Flag registers (PIR1, PIR2, PIR3, PIR4 and PIR5). REGISTER 9-4: Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE/GIEH of the INTCON register.
PIC18(L)F2X/4XK22 REGISTER 9-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by so
PIC18(L)F2X/4XK22 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IF BCL2IF RC2IF TX2IF CTMUIF TMR5GIF TMR3GIF TMR1GIF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SSP2IF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Wait
PIC18(L)F2X/4XK22 REGISTER 9-7: PIR4: PERIPHERAL INTERRUPT (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IF CCP4IF CCP3IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IF: CCP5 Interrupt Flag bits Capture mode: 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR registe
PIC18(L)F2X/4XK22 REGISTER 9-8: PIR5: PERIPHERAL INTERRUPT (FLAG) REGISTER 5 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — TMR6IF TMR5IF TMR4IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred bit 1 TMR
PIC18(L)F2X/4XK22 9.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3, PIE4 and PIE5). When IPEN = 0, the PEIE/GIEL bit must be set to enable any of these peripheral interrupts.
PIC18(L)F2X/4XK22 REGISTER 9-10: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5
PIC18(L)F2X/4XK22 REGISTER 9-11: PIE3: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IE BCL2IE RC2IE TX2IE CTMUIE TMR5GIE TMR3GIE TMR1GIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 BCL2IE: Bus Collision Interrupt Enable bit 1 = Enabled 0 = Disabled bit
PIC18(L)F2X/4XK22 REGISTER 9-12: PIE4: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IE CCP4IE CCP3IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IE: CCP5 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: C
PIC18(L)F2X/4XK22 9.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are five Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3, IPR4 and IPR5). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18(L)F2X/4XK22 REGISTER 9-15: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = L
PIC18(L)F2X/4XK22 REGISTER 9-16: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1GIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SSP2IP: Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision 2 Interrupt Priority bit 1
PIC18(L)F2X/4XK22 REGISTER 9-17: IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — CCP5IP CCP4IP CCP3IP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2 CCP5IP: CCP5 Interrupt Priority bit 1 = High priority 0 = Low priority bit 1 CCP4IP: CCP4 Interrupt Priority bit 1 = High priority 0 = Low priorit
PIC18(L)F2X/4XK22 9.8 INTn Pin Interrupts 9.9 External interrupts on the RB0/INT0, RB1/INT1 and RB2/INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18(L)F2X/4XK22 TABLE 9-1: Name ANSELB INTCON REGISTERS ASSOCIATED WITH INTERRUPTS Bit 7 Bit 6 — — GIE/GIEH PEIE/GIEL Bit 2 Bit 1 Bit 0 Register on Page ANSB3 ANSB2 ANSB1 ANSB0 153 RBIE TMR0IF INT0IF RBIF 115 — TMR0IP — RBIP 116 INT1IE — INT2IF INT1IF 117 Bit 5 Bit 4 Bit 3 ANSB5 ANSB4 TMR0IE INT0IE INTCON2 RBPU INTEDG0 INTCON3 INT2IP INT1IP INTEDG1 INTEDG2 — INT2IE IOCB IOCB7 IOCB6 IOCB5 IOCB4 — — — — 156 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP T
PIC18(L)F2X/4XK22 10.0 I/O PORTS 10.1 Depending on the device selected and features enabled, there are up to five ports available. All pins of the I/O ports are multiplexed with one or more alternate functions from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has five registers for its operation.
PIC18(L)F2X/4XK22 TABLE 10-1: PORTA I/O SUMMARY Pin Name Function RA0/C12IN0-/AN0 RA0 RA1/C12IN1-/AN1 RA2/C2IN+/AN2/ DACOUT/VREF- RA3/C1IN+/AN3/ VREF+ RA4/CCP5/ C1OUT/SRQ/ T0CKI RA5/C2OUT/ SRNQ/SS1/ HLVDIN/AN4 TRIS ANSEL Setting Setting Buffer Type Description 0 1 O DIG LATA<0> data output; not affected by analog input. 1 0 I TTL PORTA<0> data input; disabled when analog input enabled. C12IN0- 1 1 I AN Comparators C1 and C2 inverting input. AN0 1 1 I AN Analog input 0.
PIC18(L)F2X/4XK22 TABLE 10-1: PORTA I/O SUMMARY (CONTINUED) Pin Name RA6/CLKO/OSC2 RA6 RA7/CLKI/OSC1 Legend: TRIS ANSEL Setting Setting Function Pin Type Buffer Type Description 0 1 O DIG LATA<6> data output; enabled in INTOSC modes when CLKO is not enabled. 1 0 I TTL PORTA<6> data input; enabled in INTOSC modes when CLKO is not enabled. CLKO x 1 O DIG In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate.
PIC18(L)F2X/4XK22 10.1.1 PORTA OUTPUT PRIORITY Each PORTA pin is multiplexed with other functions. The pins, their combined functions and their output priorities are briefly described here. For additional information, refer to the appropriate section in this data sheet. When multiple outputs are enabled, the actual pin control goes to the peripheral with the higher priority. Table 10-4 lists the PORTA pin functions from the highest to the lowest priority.
PIC18(L)F2X/4XK22 TABLE 10-4: Port bit 5 PORT PIN FUNCTION PRIORITY (CONTINUED) Port Function Priority by Port Pin PORTD(2) PORTA PORTB PORTC SRNQ CCP3(3) SDO1 P1B C2OUT P3A(3) RC5 RD5 RA5 P2B(1)(4) PORTE(2) RB5 6 OSC2 PGC TX1/CK1 TX2/CK2 CLKO TX2/CK2(1) CCP3(1)(7) P1C RB6 P3A(1)(7) RD6 ICDCK RC6 RA6 7 RA7 OSC1 RA7 PGD RX2/DT2 RX1/DT1 (1) RB7 RX2/DT2 P3B(1) P1D RC7 RD7 ICDDT Note 1: 2: 3: 4: 5: 6: 7: 8: PIC18(L)F2XK22 devices. PIC18(L)F4XK22 devices.
PIC18(L)F2X/4XK22 10.2 PORTB Registers 10.3 PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped.
PIC18(L)F2X/4XK22 10.3.3 A mismatch condition will continue to set the RBIF flag bit. Reading or writing PORTB will end the mismatch condition and allow the RBIF bit to be cleared. The latch holding the last read value is not affected by a MCLR nor Brown-out Reset. After either one of these Resets, the RBIF flag will continue to be set if a mismatch is present. Note: ALTERNATE FUNCTIONS PORTB is multiplexed with several peripheral functions (Table 10-5). The pins have TTL input buffers.
PIC18(L)F2X/4XK22 TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) Pin Function RB2/INT2/CTED1/ P1B/SDI2/SDA2/ AN8 RB2 RB4/IOC0/P1D/ T5G/AN11 RB5/IOC1/P2B/ P3A/CCP3/T3CKI/ T1G/AN13 Legend: Note 1: 2: 3: Pin Type Buffer Type Description 0 1 O DIG LATB<2> data output; not affected by analog input. 1 0 I ST PORTB<2> data input; disabled when analog input enabled. External interrupt 2. INT2 1 0 I ST CTED1 1 0 I ST CTMU Edge 1 input. P1B(3) 0 1 O DIG Enhanced CCP1 PWM output 2.
PIC18(L)F2X/4XK22 TABLE 10-5: PORTB I/O SUMMARY (CONTINUED) Pin Function RB6/KBI2/PGC TRIS ANSEL Setting Setting RB6 2: 3: ANSELB ECCP2AS O DIG LATB<6> data output; not affected by analog input. 1 0 I ST PORTB<6> data input; disabled when analog input enabled. 1 0 I TTL Interrupt-on-change pin. 0 1 O DIG EUSART 2 asynchronous transmit data output. CK2(3) 0 1 O DIG EUSART 2 synchronous serial clock output. 1 0 I ST EUSART 2 synchronous serial clock input.
PIC18(L)F2X/4XK22 TABLE 10-7: Name CONFIGURATION REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 354 CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 355 Legend: Note 1: 10.4 — = unimplemented locations, read as ‘0’. Shaded bits are not used for PORTB. Can only be changed when in high voltage programming mode.
PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY Pin Name RC0/P2B/T3CKI/T3G/ T1CKI/SOSCO RC1/P2A/CCP2/SOSCI RC2/CTPLS/P1A/ CCP1/T5CKI/AN14 Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC0 0 1 O DIG LATC<0> data output; not affected by analog input. 1 0 I ST PORTC<0> data input; disabled when analog input enabled. P2B(2) 0 1 O DIG Enhanced CCP2 PWM output 2. T3CKI(1) 1 0 I ST Timer3 clock input. Timer3 external clock gate input.
PIC18(L)F2X/4XK22 TABLE 10-8: PORTC I/O SUMMARY (CONTINUED) Pin Name RC5/SDO1/AN17 Function TRIS Setting ANSEL setting Pin Type Buffer Type Description RC5 0 1 O DIG LATC<5> data output; not affected by analog input. 1 0 I ST PORTC<5> data input; disabled when analog input enabled. 0 1 O DIG MSSP1 SPI data output. I AN Analog input 17. 0 1 O DIG LATC<6> data output; not affected by analog input. 1 0 I ST PORTC<6> data input; disabled when analog input enabled.
PIC18(L)F2X/4XK22 TABLE 10-9: Name ANSELC ECCP1AS Bit 7 Bit 6 ANSC7 ANSC6 CCP1ASE CCP1CON P1M<1:0> CCP2CON Bit 4 Bit 3 Bit 2 ANSC5 ANSC4 ANSC3 ANSC2 P1SSAC<1:0> DC1B<1:0> Bit 1 Bit 0 Register on Page — — 153 P1SSBD<1:0> CCP1M<3:0> CCP2AS<2:0> P2M<1:0> CTMUCONH Bit 5 CCP1AS<2:0> CCP2ASE ECCP2AS LATC REGISTERS ASSOCIATED WITH PORTC 201 P2SSAC<1:0> DC2B<1:0> 205 P2SSBD<1:0> CCP2M<3:0> 205 201 CTMUEN — CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG 329 LATC7 LAT
PIC18(L)F2X/4XK22 10.5 Note: PORTD Registers 10.5.1 PORTD is only available on 40-pin and 44pin devices. PORTD is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., disable the output driver). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin).
PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY Pin Name Function RD0/SCK2/SCL2/AN20 RD0 1 O DIG LATD<0> data output; not affected by analog input. 1 0 I ST PORTD<0> data input; disabled when analog input enabled. 0 1 O DIG MSSP2 SPI Clock output. 1 0 I ST MSSP2 SPI Clock input. 0 1 O DIG MSSP2 I2C™ Clock output. 1 0 I I2C MSSP2 I2C™ Clock input. AN20 1 1 I AN Analog input 20. RD1 0 1 O DIG LATD<1> data output; not affected by analog input.
PIC18(L)F2X/4XK22 TABLE 10-11: PORTD I/O SUMMARY Pin Name Function RD6/P1C/TX2/CK2/ AN26 TRIS ANSEL Pin Buffer Setting setting Type Type RD6 0 1 O DIG LATD<6> data output; not affected by analog input. 1 0 I ST PORTD<6> data input; disabled when analog input enabled. P1C 0 1 O DIG Enhanced CCP1 PWM output 3. TX2 0 1 O DIG EUSART 2 asynchronous transmit data output. CK2 0 1 O DIG EUSART 2 synchronous serial clock output. 1 0 I ST EUSART 2 synchronous serial clock input.
PIC18(L)F2X/4XK22 10.6 PORTE Registers 10.6.2 Depending on the particular PIC18(L)F2X/4XK22 device selected, PORTE is implemented in two different ways. 10.6.1 PORTE ON 40/44-PIN DEVICES For PIC18(L)F2X/4XK22 devices, PORTE is a 4-bit wide port. Three pins (RE0/P3A/CCP3/AN5, RE1/P3B/ AN6 and RE2/CCP5/AN7) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as an analog input, these pins will read as ‘0’s.
PIC18(L)F2X/4XK22 TABLE 10-14: PORTE I/O SUMMARY Pin Function RE0/P3A/CCP3/AN5 RE0 TRIS ANSEL Pin Setting Setting Type 1 O DIG LATE<0> data output; not affected by analog input. 1 0 I ST PORTE<0> data input; disabled when analog input enabled. P3A(1) 0 1 O DIG Enhanced CCP3 PWM output. CCP3(1) 0 1 O DIG Compare 3 output/PWM 3 output. RE2/CCP5/AN7 1 0 I ST Capture 3 input. AN5 1 1 I AN Analog input 5. RE1 0 1 O DIG LATE<1> data output; not affected by analog input.
PIC18(L)F2X/4XK22 TABLE 10-16: CONFIGURATION REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 CONFIG3H MCLRE — P2BMX T3CMX HFOFST CONFIG4L DEBUG XINST — — — Bit 2 Bit 1 Bit 0 CCP3MX PBADEN CCP2MX (1) LVP — STRVEN Reset Values on page 354 355 Legend: — = unimplemented locations, read as ‘0’. Shaded bits are not used for Interrupts. Note 1: Can only be changed when in high voltage programming mode. 10.7 Port Analog Control 10.
PIC18(L)F2X/4XK22 REGISTER 10-2: PORTE: PORTE REGISTER U-0 U-0 U-0 U-0 R/W-u/x R/W-u/x R/W-u/x R/W-u/x — — — — RE3(1) RE2(2), (3) RE1(2), (3) RE0(2), (3) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets bit 7-4 Unimplemented: Read as ‘0’ bit 3 RE3: PORTE Input bit value(1) bit 2-0 RE<2:0>: PORTE I/O bit values(2), (3) Note 1: 2
PIC18(L)F2X/4XK22 REGISTER 10-4: ANSELB – PORTB ANALOG SELECT REGISTER U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 ANSB<5:0>: RB<5:0> Analog Select bit 1 = Digital input buffer disabled 0 = Digital input buffer enabled REGISTER 10-5: x = Bit is unknown
PIC18(L)F2X/4XK22 REGISTER 10-7: ANSELE – PORTE ANALOG SELECT REGISTER U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 — — — — — ANSE2(1) ANSE1(1) ANSE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-3 Unimplemented: Read as ‘0’ bit 2-0 ANSE<2:0>: RE<2:0> Analog Select bit(1) 1 = Digital input buffer disabled 0 = Digital input buffer enabled Note 1: x = Bit is unknown Available on
PIC18(L)F2X/4XK22 REGISTER 10-10: LATx: PORTx OUTPUT LATCH REGISTER(1) R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u R/W-x/u LATx7 LATx6 LATx5 LATx4 LATx3 LATx2 LATx1 LATx0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared LATx<7:0>: PORTx Output Latch bit value(2) bit 7-0 Note 1: 2: x = Bit is unknown Register Description for LATA, LATB, LATC and LATD.
PIC18(L)F2X/4XK22 REGISTER 10-13: IOCB: INTERRUPT-ON-CHANGE PORTB CONTROL REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 IOCB7 IOCB6 IOCB5 IOCB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Note 1: x = Bit is unknown IOCB<7:4>: Interrupt-on-Change PORTB control bits 1 = Interrupt-on-change enabled(1) 0 = Interrupt-on-change disabled Interrupt-on-change requires tha
PIC18(L)F2X/4XK22 11.0 TIMER0 MODULE The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable.
PIC18(L)F2X/4XK22 11.1 Timer0 Operation 11.2 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write.
PIC18(L)F2X/4XK22 FIGURE 11-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Note: 11.3 Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. Prescaler 11.3.1 An 8-bit counter is available as a prescaler for the Timer0 module.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 160 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 12.
PIC18(L)F2X/4XK22 12.1 Timer1/3/5 Operation 12.2.1 When the internal clock source is selected the TMRxH:TMRxL register pair will increment on multiples of FOSC as determined by the Timer1/3/5 prescaler. The Timer1/3/5 module is a 16-bit incrementing counter which is accessed through the TMRxH:TMRxL register pair. Writes to TMRxH or TMRxL directly update the counter.
PIC18(L)F2X/4XK22 12.3 Timer1/3/5 Prescaler 12.5.1 Timer1/3/5 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. The TxCKPS bits of the TxCON register control the prescale counter. The prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to TMRxH or TMRxL. 12.4 Secondary Oscillator A dedicated secondary low-power 32.768 kHz oscillator circuit is built-in between pins SOSCI (input) and SOSCO (amplifier output).
PIC18(L)F2X/4XK22 FIGURE 12-2: TIMER1/3/5 16-BIT READ/WRITE MODE BLOCK DIAGRAM 12.7.2 The Timer1/3/5 Gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits of the TxGCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the TxGPOL bit of the TxGCON register.
PIC18(L)F2X/4XK22 12.7.2.3 Comparator C1 Gate Operation 12.7.4 The output resulting from a Comparator 1 operation can be selected as a source for Timer1/3/5 Gate Control. The Comparator 1 output (SYNCC1OUT) can be synchronized to the Timer1/3/5 clock or left asynchronous. For more information see Section 18.8.4 “Synchronizing Comparator Output to Timer1”. 12.7.2.4 Comparator C2 Gate Operation The output resulting from a Comparator 2 operation can be selected as a source for Timer1/3/5 Gate Control.
PIC18(L)F2X/4XK22 12.8 Timer1/3/5 Interrupt The Timer1/3/5 register pair (TMRxH:TMRxL) increments to FFFFh and rolls over to 0000h. When Timer1/3/5 rolls over, the Timer1/3/5 interrupt flag bit of the PIR1/2/5 register is set.
PIC18(L)F2X/4XK22 FIGURE 12-3: TIMER1/3/5 INCREMENTING EDGE TXCKI = 1 when TMRx Enabled TXCKI = 0 when TMRX Enabled Note 1: 2: Arrows indicate counter increments. In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock. FIGURE 12-4: TIMER1/3/5 GATE ENABLE MODE TMRxGE TxGPOL TxG_IN TxCKI TxGVAL Timer1/3/5 N 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 FIGURE 12-5: TIMER1/3/5 GATE TOGGLE MODE TMRxGE TxGPOL TxGTM TxTxG_IN TxCKI TxGVAL TIMER1/3/5 FIGURE 12-6: N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 TIMER1/3/5 GATE SINGLE-PULSE MODE TMRxGE TxGPOL TxGSPM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF DS41412C-page 168 N N+1 N+2 Set by hardware on falling edge of TxGVAL Cleared by software Preliminary Cleared by so
PIC18(L)F2X/4XK22 FIGURE 12-7: TIMER1/3/5 GATE SINGLE-PULSE AND TOGGLE COMBINED MODE TMRxGE TxGPOL TxGSPM TxGTM TxGGO/ Cleared by hardware on falling edge of TxGVAL Set by software DONE Counting enabled on rising edge of TxG TxG_IN TxCKI TxGVAL TIMER1/3/5 TMRxGIF N N+1 N+2 N+3 Set by hardware on falling edge of TxGVAL Cleared by software N+4 Cleared by software 12.
PIC18(L)F2X/4XK22 12.13 Timer1/3/5 Control Register The Timer1/3/5 Control register (TxCON), shown in Register 12-1, is used to control Timer1/3/5 and select the various features of the Timer1/3/5 module.
PIC18(L)F2X/4XK22 12.14 Timer1/3/5 Gate Control Register The Timer1/3/5 Gate Control register (TxGCON), shown in Register 12-2, is used to control Timer1/3/5 Gate.
PIC18(L)F2X/4XK22 TABLE 12-6: Name ANSELB REGISTERS ASSOCIATED WITH TIMER1/3/5 AS A TIMER/COUNTER Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 153 153 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 127 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 128 IPR3 SSP
PIC18(L)F2X/4XK22 13.0 TIMER2/4/6 MODULE There are three identical 8-bit Timer2-type modules available. To maintain pre-existing naming conventions, the Timers are called Timer2, Timer4 and Timer6 (also Timer2/4/6). Note: The ‘x’ variable used in this section is used to designate Timer2, Timer4, or Timer6. For example, TxCON references T2CON, T4CON, or T6CON. PRx references PR2, PR4, or PR6.
PIC18(L)F2X/4XK22 13.1 Timer2/4/6 Operation 13.2 The clock input to the Timer2/4/6 module is the system instruction clock (FOSC/4). TMRx increments from 00h on each clock edge. A 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. These options are selected by the prescaler control bits, TxCKPS<1:0> of the TxCON register. The value of TMRx is compared to that of the Period register, PRx, on each clock cycle.
PIC18(L)F2X/4XK22 REGISTER 13-1: U-0 TxCON: TIMER2/TIMER4/TIMER6 CONTROL REGISTER R/W-0 — R/W-0 R/W-0 R/W-0 TxOUTPS<3:0> R/W-0 R/W-0 TMRxON bit 7 R/W-0 TxCKPS<1:0> bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 Unimplemented: Read as ‘0’ bit 6-3 TxOUTPS<3:0>: TimerX Output Postscaler Select bits 0000 = 1:1 Postsc
PIC18(L)F2X/4XK22 TABLE 13-1: Name SUMMARY OF REGISTERS ASSOCIATED WITH TIMER2/4/6 Bit 7 CCPTMRS0 Bit 6 C3TSEL<1:0> Bit 5 — Bit 4 Bit 3 C2TSEL<1:0> — — — — GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE IPR1 — ADIP RC1IP TX1IP IPR5 — — — — PIE1 — ADIE RC1IE TX1IE CCPTMRS1 INTCON Bit 2 — C5TSEL<1:0> Bit 1 Bit 0 Register on Page C1TSEL<1:0> 204 C4TSEL<1:0> 204 TMR0IF INT0IF RBIF 115 SSP1IP CCP1IP TMR2IP TMR1IP 127 — TMR6IP TMR5IP TMR4IP 130 SSP1IE CCP1IE TMR2I
PIC18(L)F2X/4XK22 14.0 CAPTURE/COMPARE/PWM MODULES The Capture/Compare/PWM module is a peripheral which allows the user to time and control different events, and to generate Pulse-Width Modulation (PWM) signals. In Capture mode, the peripheral allows the timing of the duration of an event. The Compare mode allows the user to trigger an external event when a predetermined amount of time has expired. The PWM mode can generate Pulse-Width Modulated signals of varying frequency and duty cycle.
PIC18(L)F2X/4XK22 14.1 Capture Mode The Capture mode function described in this section is identical for all CCP and ECCP modules available on this device family. Capture mode makes use of the 16-bit Timer resources, Timer1, Timer3 and Timer5. The timer resources for each CCP capture function are independent and are selected using the CCPTMRS0 and CCPTMRS1 registers.
PIC18(L)F2X/4XK22 14.1.4 CCP PRESCALER 14.1.5 There are four prescaler settings specified by the CCPxM<3:0> bits of the CCPxCON register. Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. Any Reset will clear the prescaler counter. Capture mode requires a 16-bit TimerX module for use as a time base. There are four options for driving the 16-bit TimerX module in Capture mode.
PIC18(L)F2X/4XK22 TABLE 14-3: REGISTERS ASSOCIATED WITH CAPTURE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 124 PIE4 — — — — — CCP5IE CCP4IE CCP3IE 126 PIR1 — ADIF RC1IF TX1IF SSP1IF CCP1IF TMR2IF TMR1IF 118 PIR2 OSCFIF C1IF C2IF EEIF BCL1IF HLVDIF TMR3IF CCP2IF 119 PIR4 — — — — — CCP5IF CCP4IF CCP3IF 121 PMD0 UART2MD UART1MD TMR6MD TMR5MD TMR4MD TMR3MD T
PIC18(L)F2X/4XK22 14.2 Compare Mode 14.2.1 The Compare mode function described in this section is identical for all CCP and ECCP modules available on this device family. Compare mode makes use of the 16-bit TimerX resources, Timer1, Timer3 and Timer5. The 16-bit value of the CCPRxH:CCPRxL register pair is constantly compared against the 16-bit value of the TMRxH:TMRxL register pair.
PIC18(L)F2X/4XK22 14.2.4 SPECIAL EVENT TRIGGER 14.2.5 When Special Event Trigger mode is selected (CCPxM<3:0> = 1011), and a match of the TMRxH:TMRxL and the CCPRxH:CCPRxL registers occurs, all CCPx and ECCPx modules will immediately: COMPARE DURING SLEEP The Compare mode is dependent upon the system clock (FOSC) for proper operation. Since FOSC is shut down during Sleep mode, the Compare mode will not function properly during Sleep.
PIC18(L)F2X/4XK22 TABLE 14-5: Name REGISTERS ASSOCIATED WITH COMPARE (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 127 IPR2 OSCFIP C1IP C2IP EEIP BCL1IP HLVDIP TMR3IP CCP2IP 128 IPR4 — — — — — CCP5IP CCP4IP CCP3IP 130 PIE1 — ADIE RC1IE TX1IE SSP1IE CCP1IE TMR2IE TMR1IE 123 PIE2 OSCFIE C1IE C2IE EEIE BCL1IE HLVDIE TMR3IE CCP2IE 124 PIE4 — — — — — CCP5IE CCP4IE
PIC18(L)F2X/4XK22 14.3 PWM Overview FIGURE 14-3: Pulse-Width Modulation (PWM) is a scheme that provides power to a load by switching quickly between fully on and fully off states. The PWM signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. The high portion, also known as the pulse width, can vary in time and is defined in steps.
PIC18(L)F2X/4XK22 6. 7. 14.3.5 Configure and start the 8-bit TimerX resource: • Clear the TMRxIF interrupt flag bit of the PIR2 or PIR4 register. See Note 1 below. • Configure the TxCKPS bits of the TxCON register with the Timer prescale value. • Enable the Timer by setting the TMRxON bit of the TxCON register. Enable PWM output pin: • Wait until the Timer overflows and the TMRxIF bit of the PIR2 or PIR4 register is set. See Note 1 below.
PIC18(L)F2X/4XK22 14.3.6 PWM RESOLUTION EQUATION 14-4: The resolution determines the number of available duty cycles for a given period. For example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. The maximum PWM resolution is 10 bits when PRx is 255. The resolution is a function of the PRx register value as shown by Equation 14-4.
PIC18(L)F2X/4XK22 TABLE 14-10: REGISTERS ASSOCIATED WITH STANDARD PWM Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CCP1CON P1M<1:0> DC1B<1:0> CCP1M<3:0> 201 CCP2CON P2M<1:0> DC2B<1:0> CCP2M<3:0> 201 CCP3CON P3M<1:0> DC3B<1:0> CCP3M<3:0> 201 201 CCP4CON — — DC4B<1:0> CCP4M<3:0> CCP5CON — — DC5B<1:0> CCP5M<3:0> CCPTMRS0 CCPTMRS1 C3TSEL<1:0> — C2TSEL<1:0> — 204 C4TSEL<1:0> 204 — — — — GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0
PIC18(L)F2X/4XK22 14.4 PWM (Enhanced Mode) To select an Enhanced PWM Output mode, the PxM<1:0> bits of the CCPxCON register must be configured appropriately. The enhanced PWM function described in this section is available for CCP modules ECCP1, ECCP2 and ECCP3, with any differences between modules noted. The PWM outputs are multiplexed with I/O pins and are designated PxA, PxB, PxC and PxD.
PIC18(L)F2X/4XK22 TABLE 14-12: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES ECCP Mode PxM<1:0> CCPx/PxA Yes PxC (1) Yes PxD (1) Yes(1) Single 00 Half-Bridge 10 Yes Yes No No Full-Bridge, Forward 01 Yes Yes Yes Yes Full-Bridge, Reverse 11 Yes Yes Yes Yes Note 1: Yes PxB (1) PWM Steering enables outputs in Single mode.
PIC18(L)F2X/4XK22 FIGURE 14-7: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal PxM<1:0> PRx+1 Pulse Width 0 Period 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) Delay(1) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PRx + 1) * (TMRx Prescale Value) • Pulse Width = TOSC * (CCPRxL<7:0>:
PIC18(L)F2X/4XK22 14.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCPx/PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 14-9). This mode can be used for Half-Bridge applications, as shown in Figure 14-9, or for Full-Bridge applications, where four power switches are being modulated with two PWM signals.
PIC18(L)F2X/4XK22 14.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 14-10. In the Forward mode, pin CCPx/PxA is driven to its active state, pin PxD is modulated, while PxB and PxC will be driven to their inactive state as shown in Figure 14-11. In the Reverse mode, PxC is driven to its active state, pin PxB is modulated, while PxA and PxD will be driven to their inactive state as shown Figure 14-11.
PIC18(L)F2X/4XK22 FIGURE 14-11: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period PxA (2) Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) Note 1: 2: (1) At this time, the TMRx register is equal to the PRx register. Output signal is shown as active-high. 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 14.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register.
PIC18(L)F2X/4XK22 FIGURE 14-13: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PW PxC PxD PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 14.4.3 T = TOFF – TON All signals are shown as active-high. 2: TON is the turn-on delay of power switch QC and its driver. 3: TOFF is the turn-off delay of power switch QD and its driver.
PIC18(L)F2X/4XK22 FIGURE 14-14: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PXRSEN = 0) Missing Pulse (Auto-Shutdown) Timer Overflow Timer Overflow Missing Pulse (CCPxASE not clear) Timer Overflow Timer Overflow Timer Overflow PWM Period PWM Activity Start of PWM Period Shutdown Event CCPxASE bit Shutdown Event Occurs 14.4.4 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the autoshutdown condition has been removed.
PIC18(L)F2X/4XK22 14.4.5 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 14-16: In Half-Bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18(L)F2X/4XK22 14.4.6 PWM STEERING MODE FIGURE 14-18: In Single Output mode, PWM steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins.
PIC18(L)F2X/4XK22 14.4.7 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. The CCPxM<1:0> bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled.
PIC18(L)F2X/4XK22 TABLE 14-13: REGISTERS ASSOCIATED WITH ENHANCED PWM Name ECCP1AS Bit 7 CCP1ASE CCP1CON ECCP2AS P1M<1:0> CCPTMRS0 INTCON Bit 4 Bit 3 DC1B<1:0> P2M<1:0> 205 P2SSBD<1:0> 205 P3SSBD<1:0> 205 201 201 CCP3M<3:0> C2TSEL<1:0> — Register on Page P1SSBD<1:0> CCP2M<3:0> P3SSAC<1:0> DC3B<1:0> — Bit 0 CCP1M<3:0> DC2B<1:0> C3TSEL<1:0> Bit 1 P2SSAC<1:0> CCP3AS<2:0> P3M<1:0> Bit 2 P1SSAC<1:0> CCP2AS<2:0> CCP3ASE CCP3CON Bit 5 CCP1AS<2:0> CCP2ASE CCP2CON ECCP3AS Bit 6
PIC18(L)F2X/4XK22 TABLE 14-14: CONFIGURATION REGISTERS ASSOCIATED WITH CAPTURE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page CONFIG3H MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX 354 Legend: — = Unimplemented location, read as ‘0’. Shaded bits are not used by Capture mode.
PIC18(L)F2X/4XK22 REGISTER 14-2: R/x-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER R/W-0 PxM<1:0> R/W-0 R/W-0 R/W-0 DCxB<1:0> R/W-0 R/W-0 R/W-0 CCPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Reset ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 PxM<1:0>: Enhanced PWM Output Configuration bits If CCPxM<3:2> = 00, 01, 10: (Capture/Compare modes) xx = PxA a
PIC18(L)F2X/4XK22 REGISTER 14-2: bit 3-0 CCPxCON: ENHANCED CCPx CONTROL REGISTER (CONTINUED) CCPxM<3:0>: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets the module) 0001 = Reserved 0010 = Compare mode: toggle output on match 0011 = Reserved 0100 = 0101 = 0110 = 0111 = Capture mode: every falling edge Capture mode: every rising edge Capture mode: every 4th rising edge Capture mode: every 16th rising edge 1000 = Compare mode: set output on compare match (CCPx pin is set, CCPxIF is set) 1001
PIC18(L)F2X/4XK22 REGISTER 14-3: R/W-0 CCPTMRS0: PWM TIMER SELECTION CONTROL REGISTER 0 R/W-0 U-0 R/W-0 — C3TSEL<1:0> R/W-0 C2TSEL<1:0> U-0 R/W-0 — R/W-0 C1TSEL<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 C3TSEL<1:0>: CCP3 Timer Selection bits 00 = CCP3 – Capture/Compare modes use Timer1, PWM mode
PIC18(L)F2X/4XK22 REGISTER 14-5: R/W-0 ECCPxAS: CCPX AUTO-SHUTDOWN CONTROL REGISTER R/W-0 CCPxASE R/W-0 R/W-0 CCPxAS<2:0> R/W-0 R/W-0 R/W-0 PSSxAC<1:0> R/W-0 PSSxBD<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 CCPxASE: CCPx Auto-shutdown Event Status bit if PxRSEN = 1; 1 = An Auto-shutdown event occur
PIC18(L)F2X/4XK22 REGISTER 14-6: R/W-0 PWMxCON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 PxRSEN R/W-0 R/W-0 R/W-0 R/W-0 PxDC<6:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the CCPxASE bit clears automatically once the shutdown event goes away;
PIC18(L)F2X/4XK22 15.0 15.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP1 AND MSSP2) MODULE The SPI interface supports the following modes and features: • • • • • Master SSPx (MSSPx) Module Overview The Master Synchronous Serial Port (MSSPx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18(L)F2X/4XK22 The I2C interface supports the following modes and features: Master mode Slave mode Byte NACKing (Slave mode) Limited Multi-master support 7-bit and 10-bit addressing Start and Stop interrupts Interrupt masking Clock stretching Bus collision detection General call address matching Address masking Address Hold and Data Hold modes Selectable SDAx hold times Note 1: In devices with more than one MSSP module, it is very important to pay close attention to SSPxCONx register names.
PIC18(L)F2X/4XK22 FIGURE 15-3: MSSPx BLOCK DIAGRAM (I2C™ SLAVE MODE) Internal Data Bus Read Write SSPxBUF Reg SCLx Shift Clock SSPxSR Reg SDAx MSb LSb SSPxMSK Reg Match Detect Addr Match SSPxADD Reg Start and Stop bit Detect 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.2 SPI Mode Overview The Serial Peripheral Interface (SPI) bus is a synchronous serial data communication bus that operates in Full-Duplex mode. Devices communicate in a master/slave environment where the master device initiates the communication. A slave device is controlled through a chip select known as Slave Select. The SPI bus specifies four signal connections: • • • • During each SPI clock cycle, a full-duplex data transmission occurs.
PIC18(L)F2X/4XK22 FIGURE 15-4: SPI MASTER AND MULTIPLE SLAVE CONNECTION SPI Master SCLK SCLK SDOx SDIx SDIx SDOx General I/O General I/O SSx General I/O SCLK SDIx SDOx SPI Slave #1 SPI Slave #2 SSx SCLK SDIx SDOx SPI Slave #3 SSx 15.2.1 SPI MODE REGISTERS 15.2.2 The MSSPx module has five registers for SPI mode operation.
PIC18(L)F2X/4XK22 Any serial port function that is not desired may be overridden by programming the corresponding data direction (TRIS) register to the opposite value. set. User software must clear the WCOL bit to allow the following write(s) to the SSPxBUF register to complete successfully. The MSSPx consists of a transmit/receive shift register (SSPxSR) and a buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first.
PIC18(L)F2X/4XK22 15.2.3 SPI MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx line. The master determines when the slave (Processor 2, Figure 15-5) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input).
PIC18(L)F2X/4XK22 15.2.4 15.2.5 SPI SLAVE MODE In Slave mode, the data is transmitted and received as external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCKx pin. The Idle state is determined by the CKP bit of the SSPxCON1 register.
PIC18(L)F2X/4XK22 FIGURE 15-7: SPI DAISY-CHAIN CONNECTION SPI Master SCLK SCLK SDOx SDIx SDIx SDOx General I/O SPI Slave #1 SSx SCLK SDIx SDOx SPI Slave #2 SSx SCLK SDIx SDOx SPI Slave #3 SSx FIGURE 15-8: SLAVE SELECT SYNCHRONOUS WAVEFORM SSx SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Shift register SSPxSR and bit count are reset SSPxBUF to SSPxSR SDOx bit 7 bit 6 bit 7 SDIx bit 6 bit 0 bit 0 bit 7 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF
PIC18(L)F2X/4XK22 FIGURE 15-9: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SDIx bit 0 bit 7 Input Sample SSPxIF Interrupt Flag SSPxSR to SSPxBUF Write Collision detection active FIGURE 15-10: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF Valid SDOx bit 7 bit 6 bit 5 bit 4 bit 3
PIC18(L)F2X/4XK22 15.2.6 SPI OPERATION IN SLEEP MODE In SPI Master mode, when the Sleep mode is selected, all module clocks are halted and the transmission/ reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode; in the case of the Sleep mode, all clocks are halted.
PIC18(L)F2X/4XK22 15.3 I2C MODE OVERVIEW FIGURE 15-11: The Inter-Integrated Circuit Bus (I2C) is a multi-master serial data communication bus. Devices communicate in a master/slave environment where the master devices initiate the communication. A slave device is controlled through addressing. VDD SCLK The I2C bus specifies two signal connections: • Serial Clock (SCLx) • Serial Data (SDAx) Figure 15-11 shows a typical connection between two processors configured as master and slave devices.
PIC18(L)F2X/4XK22 When one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. This detection, when used on the SCLx line, is called clock stretching. Clock stretching give slave devices a mechanism to control the flow of data. When this detection is used on the SDAx line, it is called arbitration.
PIC18(L)F2X/4XK22 15.4 I2C MODE OPERATION TABLE 15-2: All MSSPx I2C communication is byte oriented and shifted out MSb first. Six SFR registers and 2 interrupt flags interface the module with the PIC® microcontroller and user software. Two pins, SDAx and SCLx, are exercised by the module to communicate with other external I2C devices. 15.4.1 BYTE FORMAT All communication in I2C is done in 9-bit segments. A byte is sent from a master to a slave or vice-versa, followed by an Acknowledge bit sent back.
PIC18(L)F2X/4XK22 15.4.5 15.4.7 START CONDITION The I2C specification defines a Start condition as a transition of SDAx from a high-to -low state while SCLx line is high. A Start condition is always generated by the master and signifies the transition of the bus from an Idle to an active state. Figure 15-10 shows wave forms for Start and Stop conditions. A Restart is valid any time that a Stop would be valid.
PIC18(L)F2X/4XK22 15.4.9 15.5 ACKNOWLEDGE SEQUENCE The 9th SCLx pulse for any transferred byte in I2C is dedicated as an Acknowledge. It allows receiving devices to respond back to the transmitter by pulling the SDAx line low. The transmitter must release control of the line during this time to shift in the response. The Acknowledge (ACK) is an active-low signal, pulling the SDAx line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more.
PIC18(L)F2X/4XK22 15.5.2 SLAVE RECEPTION 15.5.2.2 When the R/W bit of a matching received address byte is clear, the R/W bit of the SSPxSTAT register is cleared. The received address is loaded into the SSPxBUF register and acknowledged. When the overflow condition exists for a received address, then not Acknowledge is given. An overflow condition is defined as either bit BF of the SSPxSTAT register is set, or bit SSPxOV of the SSPxCON1 register is set.
DS41412C-page 224 Preliminary SSPxOV BF SSPxIF S 1 A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 ACK 1 D7 2 D6 4 D4 5 D3 6 D2 7 D1 SSPxBUF is read Cleared by software 3 D5 Receiving Data 8 9 2 D6 First byte of data is available in SSPxBUF 1 D0 ACK D7 4 D4 5 D3 6 D2 7 D1 8 D0 SSPxOV set because SSPxBUF is still full. ACK is not sent.
2010 Microchip Technology Inc. Preliminary CKP SSPxOV BF SSPxIF 1 SCLx S A7 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 8 9 R/W=0 ACK SEN 2 D6 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 CKP is written to ‘1’ in software, releasing SCLx SSPxBUF is read Cleared by software Clock is held low until CKP is set to ‘1’ 1 D7 Receive Data 9 ACK SEN 3 D5 4 D4 5 D3 First byte of data is available in SSPxBUF 6 D2 7 D1 SSPxOV set because SSPxBUF is still full. ACK is not sent.
DS41412C-page 226 Preliminary P S ACKTIM CKP ACKDT BF SSPxIF S Receiving Address 1 3 5 6 7 8 ACK the received byte Slave software clears ACKDT to Address is read from SSBUF If AHEN = 1: SSPxIF is set 4 ACKTIM set by hardware on 8th falling edge of SCLx When AHEN=1: CKP is cleared by hardware and SCLx is stretched 2 A7 A6 A5 A4 A3 A2 A1 Receiving Data 9 2 3 4 5 6 7 ACKTIM cleared by hardware in 9th rising edge of SCLx When DHEN=1: CKP is cleared by hardware on 8th falling ed
2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.5.3 SLAVE TRANSMISSION 15.5.3.2 7-bit Transmission When the R/W bit of the incoming address byte is set and an address match occurs, the R/W bit of the SSPxSTAT register is set. The received address is loaded into the SSPxBUF register, and an ACK pulse is sent by the slave on the ninth bit. A master device can transmit a read request to a slave, and then clock data out of the slave.
2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.5.3.3 7-bit Transmission with Address Hold Enabled Setting the AHEN bit of the SSPxCON3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. Once a matching address has been clocked in, CKP is cleared and the SSPxIF interrupt is set. Figure 15-18 displays a standard waveform of a 7-bit Address Slave Transmission with AHEN enabled. 1. 2. Bus starts Idle.
2010 Microchip Technology Inc. Preliminary D/A R/W ACKTIM CKP ACKSTAT ACKDT BF SSPxIF S Receiving Address 2 4 5 6 7 8 Slave clears ACKDT to ACK address ACKTIM is set on 8th falling edge of SCLx 9 ACK When R/W = 1; CKP is always cleared after ACK R/W = 1 Received address is read from SSPxBUF 3 When AHEN = 1; CKP is cleared by hardware after receiving matching address.
PIC18(L)F2X/4XK22 15.5.4 SLAVE MODE 10-BIT ADDRESS RECEPTION 15.5.5 This section describes a standard sequence of events for the MSSPx module configured as an I2C slave in 10-bit Addressing mode. Figure 15-19 and is used as a visual reference for this description. This is a step by step process of what must be done by slave software to accomplish I2C communication. 1. 2. 3. 4. 5. 6. 7. 8. Bus starts Idle.
2010 Microchip Technology Inc.
DS41412C-page 234 Preliminary ACKTIM CKP UA ACKDT BF 2 1 5 0 6 A9 7 A8 Set by hardware on 9th falling edge 4 1 ACKTIM is set by hardware on 8th falling edge of SCLx If when AHEN = 1; on the 8th falling edge of SCLx of an address byte, CKP is cleared Slave software clears ACKDT to ACK the received byte 3 1 8 R/W = 0 9 ACK UA 2 A6 3 A5 4 A4 5 A3 6 A2 7 A1 Update to SSPxADD is not allowed until 9th falling edge of SCLx SSPxBUF can be read anytime before the next receive
2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.5.6 CLOCK STRETCHING 15.5.6.2 Clock stretching occurs when a device on the bus holds the SCLx line low effectively pausing communication. The slave may stretch the clock to allow more time to handle data or prepare a response for the master device. A master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching.
PIC18(L)F2X/4XK22 15.5.8 GENERAL CALL ADDRESS SUPPORT In 10-bit Address mode, the UA bit will not be set on the reception of the general call address. The slave will prepare to receive the second byte as data, just as it would in 7-bit mode. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master device. The exception is the general call address which can address all devices.
PIC18(L)F2X/4XK22 15.6 I2C MASTER MODE 15.6.1 Master mode is enabled by setting and clearing the appropriate SSPxM bits in the SSPxCON1 register and by setting the SSPxEN bit. In Master mode, the SCLx and SDAx lines are set as inputs and are manipulated by the MSSPx hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSPx module is disabled.
PIC18(L)F2X/4XK22 15.6.2 CLOCK ARBITRATION Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, releases the SCLx pin (SCLx allowed to float high). When the SCLx pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCLx pin is actually sampled high. When the SCLx pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and begins counting.
PIC18(L)F2X/4XK22 15.6.4 I2C MASTER MODE START by hardware; the Baud Rate Generator is suspended, leaving the SDAx line held low and the Start condition is complete. CONDITION TIMING To initiate a Start condition, the user sets the Start Enable bit, SEN, of the SSPxCON2 register. If the SDAx and SCLx pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPxADD<7:0> and starts its count.
PIC18(L)F2X/4XK22 15.6.5 I2C MASTER MODE REPEATED SSPxCON2 register will be automatically cleared and the Baud Rate Generator will not be reloaded, leaving the SDAx pin held low. As soon as a Start condition is detected on the SDAx and SCLx pins, the S bit of the SSPxSTAT register will be set. The SSPxIF bit will not be set until the Baud Rate Generator has timed out.
PIC18(L)F2X/4XK22 15.6.6 I2C MASTER MODE TRANSMISSION 15.6.6.3 Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPxBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDAx pin after the falling edge of SCLx is asserted.
2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.6.7 I2C MASTER MODE RECEPTION 15.6.7.4 Master mode reception is enabled by programming the Receive Enable bit, RCEN, of the SSPxCON2 register. Note: The MSSPx module must be in an Idle state before the RCEN bit is set or the RCEN bit will be disregarded. The Baud Rate Generator begins counting and on each rollover, the state of the SCLx pin changes (high-to-low/ low-to-high) and data is shifted into the SSPxSR.
2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 15.6.8 ACKNOWLEDGE SEQUENCE TIMING 15.6.9 A Stop bit is asserted on the SDAx pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN, of the SSPxCON2 register. At the end of a receive/transmit, the SCLx line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDAx line low. When the SDAx line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18(L)F2X/4XK22 FIGURE 15-31: STOP CONDITION RECEIVE OR TRANSMIT MODE SCLx = 1 for TBRG, followed by SDAx = 1 for TBRG after SDAx sampled high. P bit (SSPxSTAT<4>) is set. Write to SSPxCON2, set PEN PEN bit (SSPxCON2<2>) is cleared by hardware and the SSPxIF bit is set Falling edge of 9th clock TBRG SCLx SDAx ACK P TBRG TBRG TBRG SCLx brought high after TBRG SDAx asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 15.6.
PIC18(L)F2X/4XK22 15.6.13 MULTI -MASTER COMMUNICATION, BUS COLLISION AND BUS ARBITRATION Multi-Master mode support is achieved by bus arbitration. When the master outputs address/data bits onto the SDAx pin, arbitration takes place when the master outputs a ‘1’ on SDAx, by letting SDAx float high and another master asserts a ‘0’. When the SCLx pin floats high, data should be stable. If the expected data on SDAx is a ‘1’ and the data sampled on the SDAx pin is ‘0’, then a bus collision has taken place.
PIC18(L)F2X/4XK22 15.6.13.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDAx or SCLx are sampled low at the beginning of the Start condition (Figure 15-32). SCLx is sampled low before SDAx is asserted low (Figure 15-33). During a Start condition, both the SDAx and the SCLx pins are monitored. If the SDAx pin is sampled low during this count, the BRG is reset and the SDAx line is asserted early (Figure 15-34).
PIC18(L)F2X/4XK22 FIGURE 15-34: BUS COLLISION DURING START CONDITION (SCLx = 0) SDAx = 0, SCLx = 1 TBRG TBRG SDAx Set SEN, enable Start sequence if SDAx = 1, SCLx = 1 SCLx SCLx = 0 before SDAx = 0, bus collision occurs. Set BCLxIF. SEN SCLx = 0 before BRG time-out, bus collision occurs. Set BCLxIF.
PIC18(L)F2X/4XK22 15.6.13.2 Bus Collision During a Repeated Start Condition If SDAx is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 15-35). If SDAx is sampled high, the BRG is reloaded and begins counting. If SDAx goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDAx at exactly the same time.
PIC18(L)F2X/4XK22 15.6.13.3 Bus Collision During a Stop Condition The Stop condition begins with SDAx asserted low. When SDAx is sampled low, the SCLx pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPxADD and counts down to 0. After the BRG times out, SDAx is sampled. If SDAx is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 15-37).
PIC18(L)F2X/4XK22 TABLE 15-3: Name ANSELA REGISTERS ASSOCIATED WITH I2C™ OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 Register on Page Bit 0 ANSA0 (1) ANSB0 (1) 152 153 ANSELC ANSC7 ANSC6 ANSC5 ANSC4 ANSC3 ANSC2 — — 153 ANSELD ANSD7 ANSD6 ANSD5 ANSD4 ANSD3 ANSD2 ANSD1(2) ANSD0(2) 153 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 IPR1 — ADIP RC1IP
PIC18(L)F2X/4XK22 15.7 BAUD RATE GENERATOR The MSSPx module has a Baud Rate Generator available for clock generation in both I2C and SPI Master modes. The Baud Rate Generator (BRG) reload value is placed in the SSPxADD register (Register 15-6). When a write occurs to SSPxBUF, the Baud Rate Generator will automatically begin counting down. Once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. module clock line.
PIC18(L)F2X/4XK22 REGISTER 15-1: SSPxSTAT: SSPx STATUS REGISTER R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 SMP: SPI Data Input Sample bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle
PIC18(L)F2X/4XK22 REGISTER 15-2: SSPxCON1: SSPx CONTROL REGISTER 1 R/C/HS-0 R/C/HS-0 R/W-0 R/W-0 WCOL SSPxOV SSPxEN CKP R/W-0 R/W-0 R/W-0 R/W-0 SSPxM<3:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit u = Bit is unchanged x = Bit is unknown U = Unimplemented bit, read as ‘0’ -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HS = Bit is set by hardware C = User cleared bit 7 WCOL: Write Collision Detect bit Master mode: 1 = A write
PIC18(L)F2X/4XK22 REGISTER 15-2: bit 3-0 SSPxCON1: SSPx CONTROL REGISTER 1 (CONTINUED) SSPxM<3:0>: Synchronous Serial Port Mode Select bits 0000 = SPI Master mode, clock = FOSC/4 0001 = SPI Master mode, clock = FOSC/16 0010 = SPI Master mode, clock = FOSC/64 0011 = SPI Master mode, clock = TMR2 output/2 0100 = SPI Slave mode, clock = SCKx pin, SSx pin control enabled 0101 = SPI Slave mode, clock = SCKx pin, SSx pin control disabled, SSx can be used as I/O pin 0110 = I2C Slave mode, 7-bit address 0111 = I2
PIC18(L)F2X/4XK22 REGISTER 15-3: SSPxCON2: SSPx CONTROL REGISTER 2 R/W-0 R-0 R/W-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/S/HC-0 R/W/HC-0 GCEN ACKSTAT ACKDT ACKEN(1) RCEN(1) PEN(1) RSEN(1) SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared HC = Cleared by hardware S = User set bit 7 GCEN: General Call Enable bit
PIC18(L)F2X/4XK22 REGISTER 15-4: SSPxCON3: SSPx CONTROL REGISTER 3 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 ACKTIM: Acknowledge Time Status bit (I2C mode only)(3) 1 = Indicates the I2C bus is in an Acknowled
PIC18(L)F2X/4XK22 REGISTER 15-4: SSPxCON3: SSPx CONTROL REGISTER 3 (CONTINUED) DHEN: Data Hold Enable bit (I2C Slave mode only) 1 = Following the 8th falling edge of SCLx for a received data byte; slave hardware clears the CKP bit of the SSPxCON1 register and SCLx is held low. 0 = Data holding is disabled bit 0 Note 1: 2: 3: For daisy-chained SPI operation; allows the user to ignore all but the last received byte.
PIC18(L)F2X/4XK22 SSPXADD: MSSPx ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 15-6: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCLx pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave m
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 262 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 16.0 ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) The EUSART module includes the following capabilities: • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC18(L)F2X/4XK22 FIGURE 16-2: EUSART RECEIVE BLOCK DIAGRAM CREN RXx/DTx pin Baud Rate Generator Data Recovery FOSC SPBRGHx SPBRGx x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 (8) ••• 7 1 LSb 0 START RX9 ÷n BRG16 Multiplier Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR n FERR RX9D RCREGx Register 8 FIFO Data Bus RCxIF RCxIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTAx)
PIC18(L)F2X/4XK22 16.1 EUSART Asynchronous Mode 16.1.1.2 The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH mark state which represents a ‘1’ data bit, and a VOL space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC18(L)F2X/4XK22 16.1.1.5 TSR Status 16.1.1.7 The TRMT bit of the TXSTAx register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREGx. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. Note: 16.1.1.
PIC18(L)F2X/4XK22 FIGURE 16-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREGx TXx/CKx pin Start bit bit 0 bit 1 Word 1 1 TCY TXxIF bit (Interrupt Reg. Flag) bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Note: Word 2 Word 1 BRG Output (Shift Clock) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions.
PIC18(L)F2X/4XK22 16.1.2 EUSART ASYNCHRONOUS RECEIVER 16.1.2.2 The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 16-2. The data is received on the RXx/DTx pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC18(L)F2X/4XK22 16.1.2.4 Receive Interrupts 16.1.2.7 The RCxIF interrupt flag bit of the PIR1/PIR3 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCxIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC18(L)F2X/4XK22 16.1.2.9 Asynchronous Reception Set-up: 1. 16.1.2.10 Initialize the SPBRGHx:SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.3 “EUSART Baud Rate Generator (BRG)”). 2. Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. 3. Enable the serial port by setting the SPEN bit and the RXx/DTx pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 4.
PIC18(L)F2X/4XK22 FIGURE 16-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RXx/DTx pin bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 Stop bit bit 0 bit 7/8 Stop bit Word 2 RCREGx Word 1 RCREGx RCIDL Start bit Read Rcv Buffer Reg RCREGx RCxIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RXx/DTx input. The RCREGx (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set.
PIC18(L)F2X/4XK22 16.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 16-1: The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC18(L)F2X/4XK22 REGISTER 16-2: RCSTAX: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RXx/DTx and TXx/CKx pins as serial port pins) 0 = Serial port disabled (held in Reset) bi
PIC18(L)F2X/4XK22 REGISTER 16-3: BAUDCONX: BAUD RATE CONTROL REGISTER R/W-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bi
PIC18(L)F2X/4XK22 16.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCONx register selects 16-bit mode. The SPBRGHx:SPBRGx register pair determines the period of the free running baud rate timer.
PIC18(L)F2X/4XK22 TABLE 16-4: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 UART2MD UART1MD TMR6MD TMR5MD TMR4MD RCSTA1 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 273 RCSTA2 SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 273 PMD0 TMR3MD TMR2MD TMR1MD 56 SPBRG1 EUSART1 Baud R
PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 64.000 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 18.432 MHz Actual Rate % Error SPBRGx value (decimal) FOSC = 16.000 MHz Actual Rate % Error FOSC = 11.
PIC18(L)F2X/4XK22 TABLE 16-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 0, BRG16 = 1 BAUD RATE FOSC = 8.000 MHz FOSC = 4.000 MHz Actual Rate % Error SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 3.6864 MHz SPBRGHx: SPBRGx (decimal) Actual Rate % Error FOSC = 1.000 MHz SPBRGHx :SPBRGx (decimal) Actual Rate % Error SPBRGHx: SPBRGx (decimal) 207 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 1200 1199 -0.08 416 1202 0.
PIC18(L)F2X/4XK22 16.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RXx signal, the RXx signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”) which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC18(L)F2X/4XK22 16.3.2 AUTO-BAUD OVERFLOW 16.3.3.1 During the course of automatic baud detection, the ABDOVF bit of the BAUDCONx register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGHx:SPBRGx register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RXx/DTx pin.
PIC18(L)F2X/4XK22 FIGURE 16-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RXx/DTx Line RCxIF Note 1: Cleared due to User Read of RCREGx The EUSART remains in Idle while the WUE bit is set.
PIC18(L)F2X/4XK22 16.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTAx register. The Break character transmission is then initiated by a write to the TXREGx. The value of data written to TXREGx will be ignored and all ‘0’s will be transmitted.
PIC18(L)F2X/4XK22 16.4 EUSART Synchronous Mode 16.4.1.2 Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC18(L)F2X/4XK22 16.4.1.5 1. 2. 3. Synchronous Master Transmission Set-up: 4. Initialize the SPBRGHx, SPBRGx register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 16.3 “EUSART Baud Rate Generator (BRG)”). Set the RXx/DTx and TXx/CKx TRIS controls to ‘1’. Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RXx/DTx and TXx/CKx I/O pins. 5. 6. 7. FIGURE 16-10: 8. 9.
PIC18(L)F2X/4XK22 TABLE 16-7: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 CCP1IP TMR2IP TMR1IP 127 IPR1 — ADIP RC1IP TX1IP SSP1IP IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP PIE1 — ADIE RC1IE
PIC18(L)F2X/4XK22 16.4.1.6 Synchronous Master Reception Data is received at the RXx/DTx pin. The RXx/DTx pin output driver must be disabled by setting the corresponding TRIS bits when the EUSART is configured for synchronous master receive operation. In Synchronous mode, reception is enabled by setting either the Single Receive Enable bit (SREN of the RCSTAx register) or the Continuous Receive Enable bit (CREN of the RCSTAx register).
PIC18(L)F2X/4XK22 FIGURE 16-12: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) RXx/DTx pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 TXx/CKx pin (SCKP = 0) TXx/CKx pin (SCKP = 1) Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCxIF bit (Interrupt) Read RCREGx Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
PIC18(L)F2X/4XK22 16.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for Synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTAx register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTAx register configures the device as a slave.
PIC18(L)F2X/4XK22 TABLE 16-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page BAUDCON1 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 BAUDCON2 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 274 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 115 IPR1 — ADIP RC1IP TX1IP SSP1IP CCP1IP TMR2IP TMR1IP 127 IPR3 SSP2IP BCL2IP RC2IP TX2IP CTMUIP TMR5GIP TMR3GIP TMR1G
PIC18(L)F2X/4XK22 16.4.2.3 EUSART Synchronous Slave Reception 16.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 16.4.1.6 “Synchronous Master Reception”), with the following exceptions: • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode 1. 2. 3. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC18(L)F2X/4XK22 17.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The ADC voltage reference is software selectable to either VDD or a voltage applied to the external reference pins. The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC18(L)F2X/4XK22 17.1 ADC Configuration 17.1.3 When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 17.1.1 • VDD • the fixed voltage reference (FVR BUF2) • an external voltage source (VREF+) The negative voltage reference can be: PORT CONFIGURATION The A/D operation is independent of the state of the ANSx bits and the TRIS bits.
PIC18(L)F2X/4XK22 17.1.5 CONVERSION CLOCK 17.1.6 The source of the conversion clock is software selectable via the ADCS bits of the ADCON2 register. There are seven possible clock options: • • • • • • • The ADC module allows for the ability to generate an interrupt upon completion of an Analog-to-Digital Conversion. The ADC interrupt enable is the ADIE bit in the PIE1 register and the interrupt priority is the ADIP bit in the IPR1 register. The ADC interrupt flag is the ADIF bit in the PIR1 register.
PIC18(L)F2X/4XK22 17.1.7 RESULT FORMATTING The 10-bit A/D conversion result can be supplied in two formats, left justified or right justified. The ADFM bit of the ADCON2 register controls the output format. Figure 17-2 shows the two output formats.
PIC18(L)F2X/4XK22 17.2 ADC Operation 17.2.1 Figure 17-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’.
PIC18(L)F2X/4XK22 17.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 17.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample.
PIC18(L)F2X/4XK22 17.2.10 A/D CONVERSION PROCEDURE EXAMPLE 17-1: This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18(L)F2X/4XK22 17.2.11 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC.
PIC18(L)F2X/4XK22 REGISTER 17-1: bit 0 Note 1: 2: ADCON0: A/D CONTROL REGISTER 0 (CONTINUED) ADON: ADC Enable bit 1 = ADC is enabled 0 = ADC is disabled and consumes no operating current Available on PIC18(L)F4XK22 devices only. Allow greater than 15 s acquisition time when measuring the Fixed Voltage Reference.
PIC18(L)F2X/4XK22 REGISTER 17-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 ADFM — R/W-0 R/W-0 R/W-0 R/W-0 ACQT<2:0> R/W-0 R/W-0 ADCS<2:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition time select bits.
PIC18(L)F2X/4XK22 REGISTER 17-4: R/W-x ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES<9:2> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 17-5: R/W-x ADRESL: ADC RESULT REGISTER LOW (ADRESL) ADFM = 0 R/W-x ADRES<1:0> R/W-x R/
PIC18(L)F2X/4XK22 17.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 17-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 17-5.
PIC18(L)F2X/4XK22 FIGURE 17-5: ANALOG INPUT MODEL VDD Rs VA ANx RIC 1k CPIN 5 pF I LEAKAGE(1) Sampling Switch SS Rss CHOLD = 13.5 pF Discharge Switch Note 1: VDD Legend: CPIN = Input Capacitance I LEAKAGE = Leakage current at the pin due to various junctions = Interconnect Resistance RIC SS = Sampling Switch CHOLD = Sample/Hold Capacitance VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 27.0 “Electrical Characteristics”.
PIC18(L)F2X/4XK22 TABLE 17-2: Name REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 — ADCON0 — ADCON1 TRIGSEL — ADCON2 ADFM — Bit 4 Bit 3 Bit 2 CHS<4:0> — Bit 0 GO/DONE ADON PVCFG<1:0> NVCFG<1:0> ACQT<2:0> ADRESH Bit 1 ADCS<2:0> 298 299 300 A/D Result, High Byte ADRESL Register on Page 301 A/D Result, Low Byte 301 ANSELA — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 152 ANSELB — — ANSB5 ANSB4 ANSB3 ANSB2 ANSB1 ANSB0 153 ANSELC ANSC7 ANSC6 ANSC5 ANSC4
PIC18(L)F2X/4XK22 18.0 COMPARATOR MODULE FIGURE 18-1: Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC18(L)F2X/4XK22 FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM CxCH<1:0> CxON(1) 2 C12IN0- 0 C12IN1- 1 C12IN2- CxSP D CxVIN- 2 C12IN3- CxVIN+ 3 Q1 - (2),(3) EN Cx + D Q3(2) 0 DAC 1 0 FVR BUF1 1 Read or Write of CMxCON0 CxPOL Q To Interrupts (CxIF) EN CL CxR CxIN+ Q To CMxCON0 (CxOUT) CM2CON1 (MCxOUT) Reset CxSYNC CXVREF Cx Output to PWM Logic CxOE TRIS bit 0 CXRSEL D Q 1 CxOUT Timer1 Clock SYNCCxOUT - to SR Latch - to TxG MUX(4) Note 1: 2: 3: 4: When C1O
PIC18(L)F2X/4XK22 18.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC18(L)F2X/4XK22 18.4 Comparator Interrupt Operation 18.4.1 The comparator interrupt flag will be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 18-2). The first latch is updated with the comparator output value, when the CMxCON0 register is read or written. The value is latched on the third cycle of the system clock, also known as Q3.
PIC18(L)F2X/4XK22 18.5 Operation During Sleep 18.6 The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 27.0 “Electrical Characteristics”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC18(L)F2X/4XK22 REGISTER 18-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 C1ON C1OUT C1OE C1POL C1SP C1R R/W-0 R/W-0 C1CH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0 wh
PIC18(L)F2X/4XK22 REGISTER 18-2: CM2CON: COMPARATOR 2 CONTROL REGISTER R/W-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 C2ON C2OUT C2OE C2POL C2SP C2R R/W-0 R/W-0 C2CH<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0 whe
PIC18(L)F2X/4XK22 18.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 18-5. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC18(L)F2X/4XK22 18.8 Additional Comparator Features Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 18.8.1 18.8.4 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
PIC18(L)F2X/4XK22 REGISTER 18-3: CM2CON1: COMPARATOR 1 AND 2 CONTROL REGISTER R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR BUF1 routed to C1VREF inp
PIC18(L)F2X/4XK22 TABLE 18-2: Name ANSELA ANSELB REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Register on Page — — ANSA5 — ANSA3 ANSA2 ANSA1 ANSA0 152 ANSB5 ANSB4 — — CM2CON1 MC1OUT MC2OUT CM1CON0 C1ON C1OUT C1OE CM2CON0 C2ON C2OUT C2OE — VREFCON1 DACEN DACLPS DACOE VREFCON2 — — — VREFCON0 INTCON FVREN GIE/GIEH FVRST ANSB3 ANSB2 ANSB1 ANSB0 153 C1HYS C2HYS C1SYNC C2SYNC 314 C1POL C1SP C1R C1CH<1:0> C2P
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 316 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 19.0 CHARGE TIME MEASUREMENT UNIT (CTMU) • Time measurement resolution of 1 nanosecond • High precision time measurement • Time delay of external or internal signal asynchronous to system clock • Accurate current source suitable for capacitive measurement The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation.
PIC18(L)F2X/4XK22 19.1 CTMU Operation 19.1.2 The CTMU works by using a fixed current source to charge a circuit. The type of circuit depends on the type of measurement being made. In the case of charge measurement, the current is fixed, and the amount of time the current is applied to the circuit is fixed. The amount of voltage read by the A/D is then a measurement of the capacitance of the circuit. In the case of time measurement, the current, as well as the capacitance of the circuit, is fixed.
PIC18(L)F2X/4XK22 The module uses the edge Status bits to control the current source output to external analog modules (such as the A/D Converter). Current is only supplied to external modules when only one (but not both) of the Status bits is set, and shuts current off when both bits are either set or cleared. This allows the CTMU to measure current only during the interval between edges. After both Status bits are set, it is necessary to clear them before another measurement is taken.
PIC18(L)F2X/4XK22 19.3 Calibrating the CTMU Module FIGURE 19-2: The CTMU requires calibration for precise measurements of capacitance and time, as well as for accurate time delay. If the application only requires measurement of a relative change in capacitance or time, calibration is usually not necessary.
PIC18(L)F2X/4XK22 EXAMPLE 19-1: SETUP FOR CTMU CALIBRATION ROUTINES #include "p18cxxx.
PIC18(L)F2X/4XK22 EXAMPLE 19-2: CURRENT CALIBRATION ROUTINE #include "p18cxxx.h" #define COUNT 500 #define DELAY for(i=0;i
PIC18(L)F2X/4XK22 19.3.2 CAPACITANCE CALIBRATION There is a small amount of capacitance from the internal A/D Converter sample capacitor as well as stray capacitance from the circuit board traces and pads that affect the precision of capacitance measurements. A measurement of the stray capacitance can be taken by making sure the desired capacitance to be measured has been removed. The measurement is then performed using the following steps: 1. 2. 3. 4. 5. 6. Initialize the A/D Converter and the CTMU.
PIC18(L)F2X/4XK22 EXAMPLE 19-3: CAPACITANCE CALIBRATION ROUTINE #include "p18cxxx.h" #define #define #define #define bits #define #define COUNT 25 ETIME COUNT*2.5 DELAY for(i=0;i
PIC18(L)F2X/4XK22 19.4 Measuring Capacitance with the CTMU There are two separate methods of measuring capacitance with the CTMU. The first is the absolute method, in which the actual capacitance value is desired. The second is the relative method, in which the actual capacitance is not needed, rather an indication of a change in capacitance is required. 19.4.1 ABSOLUTE CAPACITANCE MEASUREMENT For absolute capacitance measurements, both the current and capacitance calibration steps found in Section 19.
PIC18(L)F2X/4XK22 EXAMPLE 19-4: ROUTINE FOR CAPACITIVE TOUCH SWITCH #include "p18cxxx.h" #define #define #define #define COUNT 500 DELAY for(i=0;i
PIC18(L)F2X/4XK22 19.5 Measuring Time with the CTMU Module It is assumed that the time measured is small enough that the capacitance, COFFSET, provides a valid voltage to the A/D Converter. For the smallest time measurement, always set the A/D Channel Select register (AD1CHS) to an unused A/D channel; the corresponding pin for which is not connected to any circuit board trace. This minimizes added stray capacitance, keeping the total circuit capacitance close to that of the A/D Converter itself (4-5 pF).
PIC18(L)F2X/4XK22 19.6 Creating a Delay with the CTMU Module An example use of this feature is for interfacing with variable capacitive-based sensors, such as a humidity sensor. As the humidity varies, the pulse width output on CTPLS will vary. The CTPLS output pin can be connected to an input capture pin and the varying pulse width is measured to determine the humidity in the application.
PIC18(L)F2X/4XK22 19.9 Effects of a Reset on CTMU 19.10 Registers Upon Reset, all registers of the CTMU are cleared. This leaves the CTMU module disabled, its current source is turned off and all configuration options return to their default settings. The module needs to be re-initialized following any Reset. There are three control registers for the CTMU: If the CTMU is in the process of taking a measurement at the time of Reset, the measurement will be lost.
PIC18(L)F2X/4XK22 REGISTER 19-2: R/W-0 CTMUCONL: CTMU CONTROL REGISTER 1 R/W-0 EDG2POL R/W-0 EDG2SEL<1:0> R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL<
PIC18(L)F2X/4XK22 REGISTER 19-3: R/W-0 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM<5:0> R/W-0 IRNG<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-2 ITRIM<5:0>: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . .
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 332 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 20.0 SR LATCH 20.2 The module consists of a single SR Latch with multiple Set and Reset inputs as well as separate latch outputs. The SR Latch module includes the following features: • • • • Programmable input selection SR Latch output is available internally/externally Selectable Q and Q output Firmware Set and Reset Latch Operation The latch is a Set-Reset Latch that does not depend on a clock source. Each of the Set and Reset inputs are active-high.
PIC18(L)F2X/4XK22 FIGURE 20-1: DIVSRCLK BLOCK DIAGRAM 3 SRCLK<2:0> Programmable SRCLK divider 1:4 to 1:512 Peripheral Clock t0 t0+4 t0+8 DIVSRCLK 4-512 cycles ...
PIC18(L)F2X/4XK22 TABLE 20-1: DIVSRCLK FREQUENCY TABLE SRCLK<2:0> Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 25.6 s 32 s 64 s 128 s 512 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.
PIC18(L)F2X/4XK22 REGISTER 20-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = SRI pin status sets SR Latch 0 = SRI pin status has no effect on SR Latch bit 6 SRSCKE:
PIC18(L)F2X/4XK22 21.0 FIXED VOLTAGE REFERENCE (FVR) The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVREN bit of the VREFCON0 register. 21.
PIC18(L)F2X/4XK22 REGISTER 21-1: VREFCON0: FIXED VOLTAGE REFERENCE CONTROL REGISTER R/W-0 R/W-0 FVREN FVRST R/W-0 R/W-1 U-0 U-0 U-0 U-0 — — — — FVRS<1:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 FVREN: Fixed Voltage Reference Enable bit 0 = Fixed Voltage Reference is disabled 1 = Fixed Voltage Ref
PIC18(L)F2X/4XK22 22.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The negative voltage source is disabled by setting the DACLPS bit in the VREFCON1 register. Clearing the DACLPS bit in the VREFCON1 register disables the positive voltage source. 22.
PIC18(L)F2X/4XK22 FIGURE 22-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) Reserved 11 10 FVR BUF1 VREF+ VSRC+ 01 00 VDD DACR<4:0> 5 R 2 R DACPSS<1:0> R DACEN DACLPS 11111 11110 R 32 Steps R 32-to-1 MUX R R R 00001 00000 DACNSS FIGURE 22-2: VREF- 1 VSS 0 DAC (To Comparator, CSM and ADC Modules) DACOUT DACOE VSRC- VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS41412C-page 340 DACOUT Prelimina
PIC18(L)F2X/4XK22 22.7 Operation During Sleep 22.8 When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the VREFCON1 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled.
PIC18(L)F2X/4XK22 REGISTER 22-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DACR<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DACR<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DACR<4:0>/(25
PIC18(L)F2X/4XK22 23.0 HIGH/LOW-VOLTAGE DETECT (HLVD) The PIC18(L)F2X/4XK22 devices have a High/Low-Voltage Detect module (HLVD). This is a programmable circuit that sets both a device voltage trip point and the direction of change from that point. If the device experiences an excursion past the trip point in that direction, an interrupt flag is set. If the interrupt is enabled, the program execution branches to the interrupt vector address and the software responds to the interrupt.
PIC18(L)F2X/4XK22 The module is enabled by setting the HLVDEN bit (HLVDCON<4>). Each time the HLVD module is enabled, the circuitry requires some time to stabilize. The IRVST bit (HLVDCON<5>) is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and IRVST is set. trip point voltage.
PIC18(L)F2X/4XK22 23.2 HLVD Setup 23.3 To set up the HLVD module: 1. 2. 3. 4. 5. When the module is enabled, the HLVD comparator and voltage divider are enabled and consume static current. The total current consumption, when enabled, is specified in Section 27.0 “Electrical Characteristics”. Depending on the application, the HLVD module does not need to operate constantly. To reduce current requirements, the HLVD circuitry may only need to be enabled for short periods where the voltage is checked.
PIC18(L)F2X/4XK22 FIGURE 23-3: HIGH-VOLTAGE DETECT OPERATION (VDIRMAG = 1) CASE 1: HLVDIF may not be set VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST HLVDIF cleared in software Internal Reference is stable CASE 2: VHLVD VDD HLVDIF Enable HLVD TIRVST IRVST Internal Reference is stable HLVDIF cleared in software HLVDIF cleared in software, HLVDIF remains set since HLVD condition still exists Applications FIGURE 23-4: In many applications, it is desirable to detect a drop below, or rise above, a partic
PIC18(L)F2X/4XK22 23.6 Operation During Sleep 23.7 When enabled, the HLVD circuitry continues to operate during Sleep. If the device voltage crosses the trip point, the HLVDIF bit will be set and the device will wake-up from Sleep. Device execution will continue from the interrupt vector address if interrupts have been globally enabled. TABLE 23-1: Effects of a Reset A device Reset forces all registers to their Reset state. This forces the HLVD module to be turned off.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 348 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 24.0 SPECIAL FEATURES OF THE CPU 24.1 PIC18(L)F2X/4XK22 devices include several features intended to maximize reliability and minimize cost through elimination of external components. These are: Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h.
PIC18(L)F2X/4XK22 TABLE 24-1: Address CONFIGURATION BITS AND DEVICE IDs Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default/ Unprogrammed Value — — — — 0000 0000 300000h CONFIG1L — — — — 300001h CONFIG1H IESO FCMEN PRICLKEN PLLCFG 300002h CONFIG2L — — — 300003h CONFIG2H — — 300004h CONFIG3L — — — — — 300005h CONFIG3H MCLRE — P2BMX T3CMX HFOFST 300006h CONFIG4L DEBUG XINST — — — LVP(1) — STRVEN 1000 0101 300007h CONFIG4H — — — — —
PIC18(L)F2X/4XK22 REGISTER 24-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 R/P-0 IESO FCMEN PRICLKEN PLLCFG R/P-0 R/P-1 R/P-0 R/P-1 FOSC<3:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 IESO(1): Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN(1): Fail-Safe Clock Monitor E
PIC18(L)F2X/4XK22 REGISTER 24-2: CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 U-0 U-0 — — — R/P-1 R/P-1 BORV<1:0>(1) R/P-1 R/P-1 BOREN<1:0>(2) R/P-1 PWRTEN(2) bit 7 bit 0 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.9V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.
PIC18(L)F2X/4XK22 REGISTER 24-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 — — R/P-1 R/P-1 R/P-1 R/P-1 WDTPS<3:0> R/P-1 R/P-1 WDTEN<1:0> bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5-2 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:51
PIC18(L)F2X/4XK22 REGISTER 24-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 MCLRE — P2BMX T3CMX HFOFST CCP3MX PBADEN CCP2MX bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RE3 input pin disabled 0 = RE3 input pin enabled; MCLR disabled bit 6 Unimplemented: Read as ‘0’ bit 5 P2BMX:
PIC18(L)F2X/4XK22 REGISTER 24-5: R/P-1 DEBUG CONFIG4L: CONFIGURATION REGISTER 4 LOW R/P-0 (2) XINST U-0 U-0 — — U-0 — R/P-1 LVP (1) U-0 R/P-1 — STVREN bit 0 bit 7 Legend: R = Readable bit P = Programmable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed x = Bit is unknown bit 7 DEBUG: Background Debugger Enable bit(2) 1 = Background debugger disabled, RB6 and RB7 configured as general purpose I/O pins 0 = Background debugger enabled, RB6 and RB7 are dedicate
PIC18(L)F2X/4XK22 REGISTER 24-7: CONFIG5H: CONFIGURATION REGISTER 5 HIGH R/C-1 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 CPD CPB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 CPD: Data EEPROM Code Protection bit 1 = Data EEPROM not code-protected 0 = Data EEPROM code-protected bit 6 CPB: Boot Block Code Protection bit 1 = Boot Block not code-protected 0 = Boot Block code-protected bit 5-
PIC18(L)F2X/4XK22 REGISTER 24-9: R/C-1 CONFIG6H: CONFIGURATION REGISTER 6 HIGH R/C-1 WRTD WRTB R-1 (1) WRTC U-0 U-0 U-0 U-0 U-0 — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 WRTD: Data EEPROM Write Protection bit 1 = Data EEPROM not write-protected 0 = Data EEPROM write-protected bit 6 WRTB: Boot Block Write Protection bit 1 = Boot Block not write-protected 0 = Boot Block write-pr
PIC18(L)F2X/4XK22 REGISTER 24-11: CONFIG7H: CONFIGURATION REGISTER 7 HIGH U-0 R/C-1 U-0 U-0 U-0 U-0 U-0 U-0 — EBTRB — — — — — — bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7 Unimplemented: Read as ‘0’ bit 6 EBTRB: Boot Block Table Read Protection bit 1 = Boot Block not protected from table reads executed in other blocks 0 = Boot Block protected from table reads executed in other blocks bit
PIC18(L)F2X/4XK22 TABLE 24-2: DEVICE ID TABLE FOR THE PIC18(L)F2X/4XK22 FAMILY DEV<10:3> 0101 0100 0101 0101 0101 0110 0101 0111 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 24.2 Watchdog Timer (WDT) For PIC18(L)F2X/4XK22 devices, the WDT is driven by the LFINTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LFINTOSC oscillator. The 4 ms period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration Register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18(L)F2X/4XK22 24.2.1 CONTROL REGISTER Register 24-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT.
PIC18(L)F2X/4XK22 24.3 Program Verification and Code Protection Each of the blocks has three code protection bits associated with them. They are: The overall structure of the code protection on the PIC18 Flash devices differs significantly from other PIC® microcontroller devices. The user program memory is divided into three or five blocks, depending on the device. One of these is a Boot Block of 0.5K or 2K bytes, depending on the device.
PIC18(L)F2X/4XK22 24.3.1 PROGRAM MEMORY CODE PROTECTION The program memory may be read to or written from any location using the table read and table write instructions. The device ID may be read with table reads. The Configuration registers may be read and written with the table read and table write instructions. instruction that executes from a location outside of that block is not allowed to read and will result in reading ‘0’s.
PIC18(L)F2X/4XK22 FIGURE 24-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh TBLRD* WRT1, EBTR1 = 11 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18(L)F2X/4XK22 24.3.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 24.3.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 366 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 25.0 INSTRUCTION SET SUMMARY PIC18(L)F2X/4XK22 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of 8 new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 25.
PIC18(L)F2X/4XK22 TABLE 25-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18(L)F2X/4XK22 FIGURE 25-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111
PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f
PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, d, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None
PIC18(L)F2X/4XK22 TABLE 25-2: PIC18(L)F2X/4XK22 INSTRUCTION SET (CONTINUED) Mnemonic, Operands Description Cycles 16-Bit Instruction Word MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtr
PIC18(L)F2X/4XK22 25.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18(L)F2X/4XK22 ADDWFC ADD W and CARRY bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the CARRY flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/4XK22 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if CARRY bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F2X/4XK22 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if NEGATIVE bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18(L)F2X/4XK22 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if CARRY bit is ‘0’ (PC) + 2 + 2n PC Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0011 nnnn nnnn Encoding: 1110 If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/4XK22 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if OVERFLOW bit is ‘0’ (PC) + 2 + 2n PC Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the OVERFLOW bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/4XK22 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a two-cycle instruction.
PIC18(L)F2X/4XK22 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18(L)F2X/4XK22 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F2X/4XK22 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the ZERO bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F2X/4XK22 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank. If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 25.2.
PIC18(L)F2X/4XK22 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F2X/4XK22 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of
PIC18(L)F2X/4XK22 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4>; else (W<7:4>) + DC W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 DAW adjusts the eight-bit value in W, result
PIC18(L)F2X/4XK22 Decrement f, skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None DECFSZ Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/4XK22 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Description: Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No operation
PIC18(L)F2X/4XK22 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/4XK22 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the eight-bit literal ‘k’. The result is placed in W.
PIC18(L)F2X/4XK22 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18(L)F2X/4XK22 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLW k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) 1100 1111 Description: ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18(L)F2X/4XK22 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The eight-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
PIC18(L)F2X/4XK22 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18(L)F2X/4XK22 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F2X/4XK22 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18(L)F2X/4XK22 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18(L)F2X/4XK22 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged.
PIC18(L)F2X/4XK22 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18(L)F2X/4XK22 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/4XK22 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F2X/4XK22 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
PIC18(L)F2X/4XK22 SUBLW Subtract W from literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the eight-bit literal ‘k’. The result is placed in W.
PIC18(L)F2X/4XK22 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method).
PIC18(L)F2X/4XK22 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Example2: Status Affected: None Encoding: 0000 0000 0000 *+ ; Before Instruction TABLAT TBLPTR ME
PIC18(L)F2X/4XK22 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After
PIC18(L)F2X/4XK22 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a two-cycle instruction.
PIC18(L)F2X/4XK22 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank.
PIC18(L)F2X/4XK22 25.2 Extended Instruction Set A summary of the instructions in the extended instruction set is provided in Table 25-3. Detailed descriptions are provided in Section 25.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 25-1 apply to both the standard and extended PIC18 instruction sets. In addition to the standard 75 instructions of the PIC18 instruction set, PIC18(L)F2X/4XK22 devices also provide an optional extension to the core CPU functionality.
PIC18(L)F2X/4XK22 25.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18(L)F2X/4XK22 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
PIC18(L)F2X/4XK22 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) 1110 1111 Description 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18(L)F2X/4XK22 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSR(f) – k FSRf Status Affected: None Encoding: 1110 FSR2 – k FSR2 (TOS) PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18(L)F2X/4XK22 25.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 5.5.1 “Indexed Addressing with Literal Offset”).
PIC18(L)F2X/4XK22 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value
PIC18(L)F2X/4XK22 25.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F2X/4XK22 family of devices. This includes the MPLAB C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18(L)F2X/4XK22 26.0 DEVELOPMENT SUPPORT 26.
PIC18(L)F2X/4XK22 26.2 MPLAB C Compilers for Various Device Families The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.
PIC18(L)F2X/4XK22 26.7 MPLAB SIM Software Simulator 26.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18(L)F2X/4XK22 26.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express 26.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers.
PIC18(L)F2X/4XK22 27.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, and MCLR) ..................................................
PIC18(L)F2X/4XK22 FIGURE 27-1: PIC18(L)F46K22 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL TEMPERATURE) 5.5V 3.6V 3.5V 3.0V Voltage 2.7V 2.2V 1.8V 10 20 30 32 40 50 60 64 Frequency (MHz) Note 1: Maximum Frequency 20 MHz, 1.8V to 3.0V, -40°C to +85°C (PIC18(L)F2X/4XK22). 2: Maximum Frequency 64 MHz, 3.0V to 3.6V, -40°C to +85°C (PIC18LF2X/4XK22). 3: Maximum Frequency 64 MHz, 3.0V to 5.5V, -40°C to +85°C (PIC18F2X/4XK22).
PIC18(L)F2X/4XK22 27.1 DC Characteristics: Supply Voltage, PIC18(L)F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18(L)F2X/4XK22 Param Symbol No.
PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No.
PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No.
PIC18(L)F2X/4XK22 27.2 DC Characteristics: Power-Down Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Typ Typ Max Max +25°C +60°C +85°C +125°C D017 Device Characteristics DAC D018 FVR Note 1: 2: 3: Units Conditions VDD Notes 12 20 20 A 1.8V 20 30 30 A 3.
PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics Supply Current (IDD)(1),(2) D020 D021 D022 D023 D024 Typ Max Units Conditions 5.0 14 A -40°C 4.0 14 A +25°C 4.0 — A +60°C 4.
PIC18(L)F2X/4XK22 27.3 DC Characteristics: RC Run Supply Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics D035 Typ Max Units 1.0 1.7 mA -40°C to +125°C VDD = 1.8V 2.8 mA -40°C to +125°C VDD = 3.0V 1.7 D036 Conditions D037 1.2 1.
PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics Typ Supply Current (IDD)(1),(2) 2.5 Max Units Conditions 8 A -40°C 1.5 8 A +25°C 1.5 — A +60°C 2.0 10 A +85°C 4.0 25 A +125°C 3.
PIC18(L)F2X/4XK22 27.4 DC Characteristics: RC Idle Supply Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics Typ Max Units 0.3 0.50 mA -40°C to +125°C VDD = 1.8V D058 0.4 0.70 mA -40°C to +125°C VDD = 3.0V D059 0.45 0.
PIC18(L)F2X/4XK22 27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics Typ Max Units Supply Current (IDD)(1),(2) 0.07 0.14 mA -40°C to +125°C VDD = 1.8V 0.12 0.25 mA -40°C to +125°C VDD = 3.0V D072 0.08 0.
PIC18(L)F2X/4XK22 27.5 DC Characteristics: Primary Run Supply Current, PIC18(L)F2X/4XK22 (Continued) PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics D089 D090 Note 1: 2: Typ Max Units Conditions 6.8 11 mA -40°C to +125°C VDD = 3.0V 7.5 13 mA -40°C to +125°C VDD = 5.
PIC18(L)F2X/4XK22 27.6 DC Characteristics: Primary Idle Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. Device Characteristics Supply Current (IDD)(1),(2) D100 Typ Max Units Conditions 0.025 0.07 mA -40°C to +125°C VDD = 1.8V D101 0.045 0.10 mA -40°C to +125°C VDD = 3.
PIC18(L)F2X/4XK22 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No. D130 Device Characteristics Typ Supply Current (IDD)(1),(2) 4.0 14 A -40°C 4.5 14 A +25°C 5.0 — A +60°C 5.5 18 A +85°C 9.0 30 A +125°C 7.
PIC18(L)F2X/4XK22 27.7 DC Characteristics: Secondary Oscillator Supply Current, PIC18(L)F2X/4XK22 PIC18LF2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C PIC18F2X/4XK22 Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param No.
PIC18(L)F2X/4XK22 27.8 DC Characteristics:Input/Output Characteristics, PIC18(L)F2X/4XK22 DC CHARACTERISTICS Param Symbol No.
PIC18(L)F2X/4XK22 27.8 DC Characteristics:Input/Output Characteristics, PIC18(L)F2X/4XK22 (Continued) DC CHARACTERISTICS Param Symbol No. D158 Characteristic IPU Weak Pull-up Current IPURB PORTB weak pull-up current VOL Output Low Voltage Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Min Units Conditions 90 A VDD = 3.0V, VPIN = VSS Typ† Max D159 I/O ports — V IOL = 8.5 mA, VDD = 3.
PIC18(L)F2X/4XK22 27.9 Memory Programming Requirements Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C DC CHARACTERISTICS Param No.
PIC18(L)F2X/4XK22 27.10 Analog Characteristics TABLE 27-1: COMPARATOR SPECIFICATIONS Operating Conditions: 1.8V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Param No.
PIC18(L)F2X/4XK22 FIGURE 27-3: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS VDD (HLVDIF can be cleared by software) VHLVD (HLVDIF set by hardware) HLVDIF TABLE 27-4: HIGH/LOW-VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Param Symbol No. Characteristic HLVDL<3:0> Min Typ† Max Units HLVD Voltage on VDD Transition High-toLow 0000 1.80 V 0001 2.05 V 0010 2.25 V 0011 2.40 V 0100 2.50 V 0101 2.
PIC18(L)F2X/4XK22 27.11 AC (Timing) Characteristics 27.11.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 2.
PIC18(L)F2X/4XK22 27.11.2 TIMING CONDITIONS The temperature and voltages specified in Table 27-5 apply to all timing specifications unless otherwise noted. Figure 27-4 specifies the load conditions for the timing specifications. TABLE 27-5: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS FIGURE 27-4: Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C TA +125°C Operating voltage VDD range as described in DC spec Section 27.1 and Section 27.9.
PIC18(L)F2X/4XK22 27.11.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 27-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 3 4 4 2 CLKOUT TABLE 27-6: Param. No. 1A EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period (1) Min Max Units Conditions DC DC 0.
PIC18(L)F2X/4XK22 TABLE 27-7: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 5.5V) Param. No. Sym F10 FOSC Oscillator Frequency Range F11 FSYS Characteristic Min On-Chip VCO System Frequency Typ† Max Units Conditions 4 — 5 MHz VDD = 1.8-3.0V 4 — 16 MHz VDD = 3.0-3.6V, -40°C to +125°C PIC18LF2X/4XK22 4 — 16 MHz VDD = 3.0-5.5V, -40°C to +125°C PIC18F2X/4XK22 16 — 20 MHz VDD = 1.8-3.0V 16 — 64 MHz VDD = 3.0-3.6V, -40°C to +125°C PIC18LF2X/4XK22 16 — 64 MHz VDD = 3.0-5.
PIC18(L)F2X/4XK22 FIGURE 27-6: CLKOUT AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKOUT 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) Note: 20, 21 Refer to Figure 27-4 for load conditions. TABLE 27-9: Param. No.
PIC18(L)F2X/4XK22 FIGURE 27-7: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 27-4 for load conditions. FIGURE 27-8: VDD BROWN-OUT RESET TIMING BVDD 35 VBGAP = 1.2V VIVRST Enable Internal Reference Voltage Internal Reference Voltage Stable DS41412C-page 446 36 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 TABLE 27-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET REQUIREMENTS Param. Symbol No. Characteristic Min Typ Max Units 2 — — s Conditions 30 TmcL MCLR Pulse Width (low) 31 TWDT Watchdog Timer Time-out Period (no postscaler) 3.5 4.1 4.7 ms 1:1 prescaler 32 TOST Oscillation Start-up Timer Period 1024 TOSC — 1024 TOSC — TOSC = OSC1 period 33 TPWRT Power-up Timer Period 54.8 64.4 74.
PIC18(L)F2X/4XK22 TABLE 27-11: TIMER0 AND TIMER1/3/5 EXTERNAL CLOCK REQUIREMENTS Param. No. 40 Symbol Characteristic Tt0H T0CKI High Pulse Width No prescaler Min Max Units 0.5 TCY + 20 — ns 10 — ns 0.5 TCY + 20 — ns 10 — ns TCY + 10 — ns Greater of: 20 ns or (TCY + 40)/N — ns With prescaler 41 Tt0L T0CKI Low Pulse Width No prescaler With prescaler 42 Tt0P T0CKI Period No prescaler With prescaler 45 Tt1H TxCKI High Time Synchronous, no prescaler 0.
PIC18(L)F2X/4XK22 TABLE 27-12: CAPTURE/COMPARE/PWM REQUIREMENTS (ALL CCP MODULES) Param . Symbol No. 50 TccL 51 TccH Characteristic Min Max Units CCPx Input Low No prescaler Time With prescaler 0.5 TCY + 20 — ns 10 — ns CCPx Input High Time 0.
PIC18(L)F2X/4XK22 TABLE 27-13: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. No. Symbol Characteristic Min Max Units 70 TssL2scH, TssL2scL SS to SCK or SCK Input 71 TscH SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18(L)F2X/4XK22 TABLE 27-14: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. No. 71 Symbol TscH 71A 72 TscL 72A Characteristic Min Max Units SCK Input High Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns SCK Input Low Time (Slave mode) Continuous 1.25 TCY + 30 — ns Single Byte 40 — ns 100 — ns 1.
PIC18(L)F2X/4XK22 TABLE 27-15: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING, CKE = 0) Param. No. Symbol Characteristic Min Max Units TCY — ns 1.25 TCY + 30 — ns Single Byte 40 — ns Continuous 1.
PIC18(L)F2X/4XK22 TABLE 27-16: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. No.
PIC18(L)F2X/4XK22 TABLE 27-17: I2C™ BUS START/STOP BITS REQUIREMENTS (SLAVE MODE) Param. Symbol No.
PIC18(L)F2X/4XK22 TABLE 27-18: I2C™ BUS DATA REQUIREMENTS (SLAVE MODE) Param. Symbol No. 100 THIGH Characteristic Clock High Time Min Max Units Conditions 100 kHz mode 4.0 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Must operate at a minimum of 10 MHz 1.5 TCY — 100 kHz mode 4.7 — s Must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Must operate at a minimum of 10 MHz 1.
PIC18(L)F2X/4XK22 FIGURE 27-17: MASTER SSP I2C™ BUS START/STOP BITS TIMING WAVEFORMS SCL 93 91 90 92 SDA Stop Condition Start Condition Note: Refer to Figure 27-4 for load conditions. TABLE 27-19: MASTER SSP I2C™ BUS START/STOP BITS REQUIREMENTS Param. Symbol No.
PIC18(L)F2X/4XK22 TABLE 27-20: MASTER SSP I2C™ BUS DATA REQUIREMENTS Param. Symbol No. 100 THIGH Characteristic Min Max Units Clock High Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms mode(1) 2(TOSC)(BRG + 1) — ms Clock Low Time 100 kHz mode 2(TOSC)(BRG + 1) — ms 400 kHz mode 2(TOSC)(BRG + 1) — ms 1 MHz mode(1) 2(TOSC)(BRG + 1) — ms 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC18(L)F2X/4XK22 FIGURE 27-19: EUSART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING TXx/CKx pin 121 121 RXx/DTx pin 120 Note: 122 Refer to Figure 27-4 for load conditions. TABLE 27-21: EUSART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param. No.
PIC18(L)F2X/4XK22 TABLE 27-23: A/D CONVERTER CHARACTERISTICS:PIC18(L)F2X/4XK22 Param . Symbol No. Characteristic Min Typ Max Units Conditions A01 NR Resolution — — 10 bits -40°C to +85°C, VREF 2.0V A03 EIL Integral Linearity Error — ±0.5 — LSb -40°C to +85°C, VREF 2.0V A04 EDL Differential Linearity Error — ±0.4 — LSb -40°C to +85°C, VREF 2.0V A06 EOFF Offset Error — 0.4 — LSb -40°C to +85°C, VREF 2.0V A07 EGN Gain Error — 0.
PIC18(L)F2X/4XK22 TABLE 27-24: A/D CONVERSION REQUIREMENTS Param. Symbol No. 130 TAD 131 Characteristic A/D Clock Period Min Max Units 0.7 25.0(1) s TOSC based, -40C to +85C 0.7 4.0(1) s TOSC based, +85C to +125C FRC mode, VDD2.0V 1.0 4.0 s TCNV Conversion Time (not including acquisition time) (Note 2) 12 12 TAD s 132 TACQ Acquisition Time (Note 3) 1.
PIC18(L)F2X/4XK22 28.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and tables are not available at this time. 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 462 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 28-Lead SPDIP (300 mil) Example PIC18F25K22-E/SP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN e3 0810017 28-Lead SOIC (300 mil) Example PIC18F25K22-E/SO e3 0810017 XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example 28-Lead SSOP PIC18F25K22 -E/SS e3 0810017 XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN (6mm x 6mm) Example XXXXXXXX XXXXXXXX YYWWNNN Legend: XX...
PIC18(L)F2X/4XK22 Package Marking Information (Continued) 28-Lead UQFN (4mm x 4mm) Example XXXXX XXXXXX XXXXXX YWWNNN PIC18 F23K22 -E/MV e3 810017 40-Lead PDIP (600 mil) Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN PIC18F45K22-E/P e3 0810017 40-Lead UQFN (5mm x 5mm) Example XXXXXXX XXXXXXX XXXXXXX YYWWNNN PIC18 F45K22 -I/MV e3 0810017 44-Lead QFN (8mm x 8mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC18 F45K22 -E/ML e3 0810017 44-Lead TQFP (10mm x 10mm)
PIC18(L)F2X/4XK22 29.2 Package Details The following sections give the technical details of the packages. ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8.
PIC18(L)F2X/4XK22 # # $ % &'( # ) ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 NOTE 1 1 2 3 e b h α h c φ A2 A L A1 β L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7: 7 ; < & : 8 & = = = = = - # # 4 4 !! & # %% + 1 , : > #& . # # 4 > #& .
PIC18(L)F2X/4XK22 *+ ! " # (' # 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D N E E1 1 2 b NOTE 1 e c A2 A φ A1 L L1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; < & : 8 & = = ? < & # %% = = : > #& . < < # # 4 > #& .
PIC18(L)F2X/4XK22 , - % ! . / 010 ,-! 2 * '(( ) . * ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E b E2 2 2 1 1 K N N NOTE 1 L BOTTOM VIEW TOP VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . .
PIC18(L)F2X/4XK22 , - % ! . / 010 ,-! 2 * '(( ) . * ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41412C-page 470 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 3 0 ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 N NOTE 1 E1 1 2 3 D E A2 A L c b1 A1 b e eB 6 &! ' ! 9 ' &! 7"') % ! 7,8. 7 7 & ; & & 7: 1 , = = = 1 ! & & = = .
PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS41412C-page 474 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 33 , - % ! . / 1 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D2 EXPOSED PAD e E E2 b 2 2 1 N 1 N NOTE 1 TOP VIEW K L BOTTOM VIEW A A3 A1 6 &! ' ! 9 ' &! 7"') % ! 99 . . 7 7 7: ; & : 8 & < & # %% , & & 4 !! - : > #& . .$ .
PIC18(L)F2X/4XK22 33 , - % ! . / 1 ,-! ! " 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 33 4* ! " , - 5 4 6 16 16 % ' 4,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 D D1 E e E1 N b NOTE 1 1 2 3 NOTE 2 α A φ c β A2 A1 L L1 6 &! ' ! 9 ' &! 7"') % 9 #! 99 . .
PIC18(L)F2X/4XK22 33 4* ! " , - 5 4 6 16 16 % ' 4,- 3 & ' !& " & 4 # * !( ! ! & 4 % & & # & && 255*** ' '5 4 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 480 Preliminary 2010 Microchip Technology Inc.
PIC18(L)F2X/4XK22 APPENDIX A: REVISION HISTORY Revision A (February 2010) Initial release of this document. Revision B (April 2010) Updated Figures 2-4, 12-1 and 18-2; Updated Registers 2-2, 10-4, 10-5, 10-7, 17-2, 24-1 and 24-5; Updated Sections 10.3.2, 18.8.4, Synchronizing Comparator Output to Timer1; Updated Sections 27.2, 27-3, 27-4, 27-5, 27-6, 27-7 and 27-9; Updated Tables 27-2, 27-3, 27-4 and 27-7; Other minor corrections.
PIC18(L)F2X/4XK22 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table B-1.
PIC18(L)F2X/4XK22 INDEX A A/D Analog Port Pins, Configuring .................................. 304 Associated Registers ............................................... 304 Conversions ............................................................. 295 Converter Characteristics ........................................ 459 Discharge ................................................................. 296 Selecting and Configuring Acquisition Time ............ 292 Absolute Maximum Ratings ..........................
PIC18(L)F2X/4XK22 CALLW ............................................................................. 411 Capture Module. See Enhanced Capture/Compare/PWM (ECCP) Capture/Compare/PWM ................................................... 177 Capture/Compare/PWM (CCP) Associated Registers w/ Capture .......................................... 179, 180, 183, 187, 201 Associated Registers w/ Compare ........................... 182 Associated Registers w/ PWM ......................... 187, 200 Capture Mode .........
PIC18(L)F2X/4XK22 Operation During Idle Mode ..................................... 328 Operation During Sleep Mode ................................. 328 Customer Change Notification Service ............................ 493 Customer Notification Service .......................................... 493 Customer Support ............................................................ 493 CVREF Voltage Reference Specifications ........................ 439 D Data Addressing Modes .....................................
PIC18(L)F2X/4XK22 Transmission .................................................... 283 Synchronous Slave Mode Associated Registers, Receive ........................ 290 Reception ......................................................... 290 Transmission .................................................... 288 Extended Instruction Set ADDFSR .................................................................. 410 ADDULNK ................................................................
PIC18(L)F2X/4XK22 DCFSNZ .................................................................. 387 DECF ....................................................................... 386 DECFSZ ................................................................... 387 Extended Instruction Set .......................................... 409 General Format ........................................................ 369 GOTO ...................................................................... 388 INCF .......................
PIC18(L)F2X/4XK22 Marking .................................................................... 463 PIE Registers ................................................................... 123 PIE1 Register ................................................................... 123 PIE2 Register ................................................................... 124 PIE3 Register3 ................................................................. 125 PIE4 Register ........................................................
PIC18(L)F2X/4XK22 INTCON (Interrupt Control) ...................................... 115 INTCON2 (Interrupt Control 2) ................................. 116 INTCON3 (Interrupt Control 3) ................................. 117 IPR1 (Peripheral Interrupt Priority 1) ........................ 127 IPR2 (Peripheral Interrupt Priority 2) ........................ 128 IPR3 (Peripheral Interrupt Priority) ........................... 129 IPR4 (Peripheral Interrupt Priority) ...........................
PIC18(L)F2X/4XK22 Operation ................................................................. 162 Operation During Sleep ........................................... 166 Oscillator .................................................................. 163 Prescaler .................................................................. 163 Timer1 Gate Selecting Source .............................................. 164 TMR1H Register ...................................................... 161 TMR1L Register ...........
PIC18(L)F2X/4XK22 Two-Word Instructions Example Cases .......................................................... 75 TXCON (Timer2/4/6) Register ......................................... 175 TXREG ............................................................................. 265 TXSTA Register ............................................................... 272 BRGH Bit ................................................................. 275 V Voltage Reference (VR) Specifications ...............................
PIC18(L)F2X/4XK22 NOTES: DS41412C-page 492 Preliminary 2010 Microchip Technology Inc.
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PIC18(L)F2X/4XK22 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
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