Datasheet

PIC18(L)F1XK22
DS40001365F-page 98  2009-2016 Microchip Technology Inc.
TABLE 10-1: CAPACITOR SELECTION FOR
THE TIMER OSCILLATOR
10.5 Timer1 Interrupt
The TMR1 register pair (TMR1H:TMR1L) increments
from 0000h to FFFFh and rolls over to 0000h. The
Timer1 interrupt, if enabled, is generated on overflow,
which is latched in the TMR1IF interrupt flag bit of the
PIR1 register. This interrupt can be enabled or disabled
by setting or clearing the TMR1IE Interrupt Enable bit
of the PIE1 register.
10.6 Resetting Timer1 Using the CCP
Special Event Trigger
If either of the CCP modules is configured to use Timer1
and generate a Special Event Trigger in Compare mode
(CCP1M<3:0> or CCP2M<3:0> = 1011), this signal will
reset Timer1. The trigger from CCP2 will also start an
A/D conversion if the A/D module is enabled (see
Section 13.3.4 “Special Event Trigger” for more
information).
The module must be configured as either a timer or a
synchronous counter to take advantage of this feature.
When used this way, the CCPRH:CCPRL register pair
effectively becomes a period register for Timer1.
If Timer1 is running in Asynchronous Counter mode,
this Reset operation may not work.
In the event that a write to Timer1 coincides with a
special Event Trigger, the write operation will take
precedence.
10.7 Using Timer1 as a Real-Time Clock
Adding an external LP oscillator to Timer1 (such as the
one described in Section 10.4 “Timer1 Oscillator”
above) gives users the option to include RTC
functionality to their applications. This is accomplished
with an inexpensive watch crystal to provide an
accurate time base and several lines of application
code to calculate the time. When operating in Sleep
mode and using a battery or supercapacitor as a power
source, it can completely eliminate the need for a
separate RTC device and battery backup.
The application code routine, RTCisr, shown in
Example 10-1, demonstrates a simple method to
increment a counter at one-second intervals using an
Interrupt Service Routine. Incrementing the TMR1
register pair to overflow triggers the interrupt and calls
the routine, which increments the seconds counter by
one; additional counters for minutes and hours are
incremented on overflows of the less significant
counters.
Since the register pair is 16-bit wide, a 32.768 kHz
clock source will take two seconds to count up to
overflow. To force the overflow at the required
one-second intervals, it is necessary to pre-load it; the
simplest method is to set the MSb of TMR1H with a
BSF instruction. Note that the TMR1L register is never
preloaded or altered; doing so may introduce
cumulative error over many cycles.
For this method to be accurate, Timer1 must operate in
Asynchronous mode and the Timer1 overflow interrupt
must be enabled (PIE1<0> = 1), as shown in the
routine, RTCinit. The Timer1 oscillator must also be
enabled and running at all times.
Osc Type Freq. C1 C2
LP 32 kHz 27 pF
(1)
27 pF
(1)
Note 1: Microchip suggests these values only as
a starting point in validating the oscillator
circuit.
2: Higher capacitance increases the
stability of the oscillator but also
increases the start-up time.
3: Since each resonator/crystal has its own
characteristics, the user should consult
the resonator/crystal manufacturer for
appropriate values of external
components.
4: Capacitor values are for design guidance
only.
Note: The Special Event Triggers from the
CCP2 module will not set the TMR1IF
interrupt flag bit of the PIR1 register.