Datasheet

 2009-2016 Microchip Technology Inc. DS40001365F-page 79
PIC18(L)F1XK22
8.2 PORTB, TRISB and LATB
Registers
PORTB is an 4-bit wide, bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., disable the output driver). Clearing a
TRISB bit (= 0) will make the corresponding PORTB
pin an output (i.e., enable the output driver and put the
contents of the output latch on the selected pin).
The PORTB Data Latch register (LATB) is also memory
mapped. Read-modify-write operations on the LATB
register read and write the latched output value for
PORTB.
EXAMPLE 8-2: INITIALIZING PORTB
All PORTB pins are individually configurable as
interrupt-on-change pins. Control bits in the IOCB
register enable (when set) or disable (when clear) the
interrupt function for each pin.
When set, the RABIE bit of the INTCON register
enables interrupts on all pins which also have their
corresponding IOCB bit set. When clear, the RABIE
bit disables all interrupt-on-changes.
Only pins configured as inputs can cause this interrupt
to occur (i.e., any pin configured as an output is
excluded from the interrupt-on-change comparison).
For enabled interrupt-on-change pins, the values are
compared with the old value latched on the last read of
PORTB. The ‘mismatch’ outputs of the last read are
OR’d together to set the PORTB Change Interrupt flag
bit (RABIF) in the INTCON register.
This interrupt can wake the device from the Sleep
mode, or any of the Idle modes. The user, in the
Interrupt Service Routine, can clear the interrupt in the
following manner:
a) Any read or write of PORTB to clear the
mismatch condition (except when PORTB is the
source or destination of a MOVFF instruction).
b) Clear the flag bit, RABIF.
A mismatch condition will continue to set the RABIF flag
bit. Reading or writing PORTB will end the mismatch
condition and allow the RABIF bit to be cleared. The latch
holding the last read value is not affected by a MCLR
nor
Brown-out Reset. After either one of these Resets, the
RABIF flag will continue to be set if a mismatch is present.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
All PORTB pins have individually controlled weak
internal pull-up. When set, each bit of the WPUB
register enables the corresponding pin pull-up. When
cleared, the RABPU
bit of the INTCON2 register
enables pull-ups on all pins which also have their
corresponding WPUB bit set. When set, the RABPU
bit
disables all weak pull-ups. The weak pull-up is
automatically turned off when the port pin is configured
as an output. The pull-ups are disabled on a Power-on
Reset.
CLRF PORTB ; Initialize PORTB by
; clearing output
; data latches
CLRF LATB ; Alternate method
; to clear output
; data latches
MOVLW 0F0h ; Value used to
; initialize data
; direction
MOVWF TRISB ; Set RB<7:4> as outputs
Note: If a change on the I/O pin should occur
when the read operation is being executed
(start of the Q2 cycle), then the RABIF
interrupt flag may not get set. Furthermore,
since a read or write on a port affects all
bits of that port, care must be taken when
using multiple pins in Interrupt-on-Change
mode. Changes on one pin may not be
seen while servicing changes on another
pin.
Note: On a Power-on Reset, RB<5:4> are
configured as analog inputs by default and
read as ‘0’.