Datasheet

 2009-2016 Microchip Technology Inc. DS40001365F-page 61
PIC18(L)F1XK22
FIGURE 7-1: PIC18 INTERRUPT LOGIC
Note: Do not use the MOVFF instruction to
modify any of the interrupt control
registers while any interrupt is enabled.
Doing so may cause erratic
microcontroller behavior.
TMR0IE
GIEH/GIE
GIEL/PEIE
Wake-up if in
Interrupt to CPU
Vector to Location
0008h
INT2IF
INT2IE
INT2IP
INT1IF
INT1IE
INT1IP
TMR0IF
TMR0IE
TMR0IP
RABIF
RABIE
RABIP
IPEN
TMR0IF
TMR0IP
INT1IF
INT1IE
INT1IP
INT2IF
INT2IE
INT2IP
RABIF
RABIE
RABIP
INT0IF
INT0IE
GIEL/PEIE
Interrupt to CPU
Vector to Location
IPEN
IPEN
0018h
SSPIF
SSPIE
SSPIP
SSPIF
SSPIE
SSPIP
ADIF
ADIE
ADIP
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
ADIF
ADIE
ADIP
High Priority Interrupt Generation
Low Priority Interrupt Generation
RCIF
RCIE
RCIP
Additional Peripheral Interrupts
Idle or Sleep modes
GIEH/GIE
Note 1: The RABIF interrupt also requires the individual pin IOCA and IOCB enable.
(1)
(1)