Datasheet

PIC18(L)F1XK22
DS40001365F-page 350  2009-2016 Microchip Technology Inc.
FIGURE 26-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING
FIGURE 26-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING
Note: Refer to Figure 26-7 for load conditions.
US121
US121
US120
US122
CK
DT
TABLE 26-24: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US120 TCKH2DTV SYNC XMIT (Master and Slave)
Clock high to data-out valid
3.0-5.5V — 80 ns
1.8-5.5V — 100 ns
US121 T
CKRF Clock out rise time and fall time
(Master mode)
3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
US122 T
DTRF Data-out rise time and fall time 3.0-5.5V — 45 ns
1.8-5.5V — 50 ns
Note: Refer to Figure 26-7 for load conditions.
US125
US126
CK
DT
TABLE 26-25: USART SYNCHRONOUS RECEIVE REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Symbol Characteristic Min. Max. Units Conditions
US125 TDTV2CKL SYNC RCV (Master and Slave)
Data-hold before CK  (DT hold time) 10 — ns
US126 T
CKL2DTL Data-hold after CK  (DT hold time) 15 — ns