Datasheet

 2009-2016 Microchip Technology Inc. DS40001365F-page 23
PIC18(L)F1XK22
FIGURE 2-7: FSCM TIMING DIAGRAM
TABLE 2-5: SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK SOURCES
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values on
page
CONFIG1H IESO FCMEN PCLKEN PLL_EN FOSC3 FOSC2 FOSC1 FOSC0 251
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245
OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 246
OSCCON2
— — — — — PRI_SD HFIOFL LFIOFS 246
OSCTUNE INTSRC PLLEN TUN5 TUN4 TUN3 TUN2 TUN1 TUN0 248
IPR2 OSCFIP
C1IP C2IP EEIP BCLIP — TMR3IP — 248
PIE2 OSCFIE
C1IE C2IE EEIE BCLIE — TMR3IE — 248
PIR2 OSCFIF
C1IF C2IF EEIF BCLIF — TMR3IF — 248
T1CON
RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 246
Legend: x = unknown, u = unchanged, – = unimplemented locations read as ‘0’. Shaded cells are not used by oscillators.
Note 1: Other (non Power-up) Resets include MCLR
Reset and Watchdog Timer Reset during normal operation.
OSCFIF
System
Clock
Output
Sample Clock
Failure
Detected
Oscillator
Failure
Note: The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
(Q)
Tes t
Test Test
Clock Monitor Output