Datasheet

 2009-2016 Microchip Technology Inc. DS40001365F-page 225
PIC18(L)F1XK22
18.4.1 PRI_IDLE MODE
This mode is unique among the three low-power Idle
modes, in that it does not disable the primary device
clock. For timing sensitive applications, this allows for
the fastest resumption of device operation with its more
accurate primary clock source, since the clock source
does not have to “warm-up” or transition from another
oscillator.
PRI_IDLE mode is entered from PRI_RUN mode by
setting the IDLEN bit and executing a SLEEP
instruction. If the device is in another Run mode, set
IDLEN first, then clear the SCS bits and execute
SLEEP. Although the CPU is disabled, the peripherals
continue to be clocked from the primary clock source
specified by the FOSC<3:0> Configuration bits. The
OSTS bit remains set (see Figure 18-3).
When a wake event occurs, the CPU is clocked from the
primary clock source. A delay of interval T
CSD is
required between the wake event and when code
execution starts. This is required to allow the CPU to
become ready to execute instructions. After the wake-
up, the OSTS bit remains set. The IDLEN and SCS bits
are not affected by the wake-up (see Figure 18-4).
18.4.2 SEC_IDLE MODE
In SEC_IDLE mode, the CPU is disabled but the
peripherals continue to be clocked from the Timer1
oscillator. This mode is entered from SEC_RUN by
setting the IDLEN bit and executing a SLEEP
instruction. If the device is in another Run mode, set the
IDLEN bit first, then set the SCS<1:0> bits to ‘01’ and
execute SLEEP. When the clock source is switched to
the Timer1 oscillator, the primary oscillator is shut
down, the OSTS bit is cleared and the T1RUN bit is set.
When a wake event occurs, the peripherals continue
to be clocked from the Timer1 oscillator. After an
interval of T
CSD following the wake event, the CPU
begins executing code being clocked by the Timer1
oscillator. The IDLEN and SCS bits are not affected by
the wake-up; the Timer1 oscillator continues to run
(see Figure 18-4).
FIGURE 18-3: TRANSITION TIMING FOR ENTRY TO IDLE MODE
FIGURE 18-4: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE
Note: The Timer1 oscillator should already be
running prior to entering SEC_IDLE
mode. If the T1OSCEN bit is not set when
the SLEEP instruction is executed, the
main system clock will continue to operate
in the previously selected mode and the
corresponding IDLE mode will be entered
(i.e., PRI_IDLE or RC_IDLE).
Q1
Peripheral
Program
PC PC + 2
OSC1
Q3
Q4
Q1
CPU Clock
Clock
Counter
Q2
OSC1
Peripheral
Program
PC
CPU Clock
Q1 Q3 Q4
Clock
Counter
Q2
Wake Event
TCSD