Datasheet

PIC18(L)F1XK22
DS40001365F-page 174  2009-2016 Microchip Technology Inc.
FIGURE 15-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 15-1: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 247
INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245
IPR1
— ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 248
PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248
PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248
RCSTA
SPEN RX9 SREN CREN ADDEN FERR OERR RX9D 247
SPBRG EUSART Baud Rate Generator Register, Low Byte 247
SPBRGH EUSART Baud Rate Generator Register, High Byte 247
TXREG
EUSART Transmit Register 247
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 247
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous transmission.
Transmit Shift Reg
Write to TXREG
BRG Output
(Shift Clock)
RB7/TX/CK
TXIF bit
(Interrupt Reg. Flag)
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin