Datasheet

 2009-2016 Microchip Technology Inc. DS40001365F-page 135
PIC18(L)F1XK22
14.2.8 OPERATION IN POWER-MANAGED
MODES
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
In all Idle modes, a clock is provided to the peripherals.
That clock could be from the primary clock source, the
secondary clock (Timer1 oscillator at 32.768 kHz) or
the INTOSC source. See Section 18.0 “Power-Man-
aged Modes” for additional information.
In most cases, the speed that the master clocks SPI
data is not important; however, this should be
evaluated for each system.
When MSSP interrupts are enabled, after the master
completes sending data, an MSSP interrupt will wake
the controller:
• From Sleep, in Slave mode
• From Idle, in Slave or Master mode
If an exit from Sleep or Idle mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the
transmission/reception will remain in that state until the
device wakes. After the device returns to Run mode,
the module will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in any Power-Managed
mode and data to be shifted into the SPI
Transmit/Receive Shift register. When all eight bits
have been received, the MSSP interrupt flag bit will be
set and if enabled, will wake the device.
14.2.9 EFFECTS OF A RESET
A Reset disables the MSSP module and terminates the
current transfer.
14.2.10 BUS MODE COMPATIBILITY
Table 14-1 shows the compatibility between the
standard SPI modes and the states of the CKP and
CKE control bits.
TABLE 14-1: SPI BUS MODES
There is also an SMP bit which controls when the data
is sampled.
TABLE 14-2: REGISTERS ASSOCIATED WITH SPI OPERATION
Standard SPI Mode
Terminology
Control Bits State
CKP CKE
0, 0 0 1
0, 1 0 0
1, 0 1 1
1, 1 1 0
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Reset
Values
on page
INTCON GIE/GIEH PEIE/GIEL
TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245
IPR1
—
ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 248
PIE1
—
ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248
PIR1
—
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248
TRISB
TRISB7 TRISB6 TRISB5 TRISB4
— — — —
248
TRISC TRISC7 TRISC6
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 248
SSPBUF SSP Receive Buffer/Transmit Register 246
SSPCON1 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 246
SSPSTAT SMP CKE
D/A P S R/W UA BF 246
Legend: Shaded cells are not used by the MSSP in SPI mode.