PIC18(L)F1XK22 20-Pin Flash Microcontrollers with XLP Technology High-Performance RISC CPU Analog Features • C Compiler Optimized Architecture: - Optional extended instruction set designed to optimize re-entrant code • 256 bytes Data EEPROM • Up to 16 Kbytes Linear Program Memory Addressing • Up to 512 bytes Linear Data Memory Addressing • Up to 16 MIPS Operation • 16-bit Wide Instructions, 8-bit Wide Data Path • Priority Levels for Interrupts • 31-Level, Software Accessible Hardware Stack • 8 x 8 Single-
PIC18(L)F1XK22 SR Latch Pins I/O(1) EUSART Data EEPROM (bytes) MSSP SRAM (bytes) ECCP Words Timers 8-bit/16-bit Bytes Data Memory Comparators Device Program Memory 10-bit A/D Channels Data Sheet Index PIC18(L)F1XK22 Family Types PIC18(L)F13K22 (1) 8K 4K 256 256 20 18 12-ch 2 1/3 1 1 1 Yes PIC18(L)F14K22 (1) 16K 8K 512 256 20 18 12-ch 2 1/3 1 1 1 Yes Note 1: One pin is input-only. Data Sheet Index: (Unshaded devices are described in this document) 1.
PIC18(L)F1XK22 18 15 AN1 C12IN0- VREF+ — — — RA2 17 14 AN2 C1OUT — — — — RA3 4 1 — — — — — — RA4 3 20 AN3 — — — — RA5 2 19 — — — — RB4 13 10 AN10 — — RB5 12 9 AN11 — — — — — — IOC/INT0 Basic RA1 — Pull-up VREF-/ CVREF(DAC1OUT) Interrupts C1IN+ Timers Reference AN0 SR Latch Comparator 16 MSSP Analog 19 EUSART 20-Pin QFN RA0 ECCP 20-Pin PDIP/SSOP/SOIC 20-PIN ALLOCATION TABLE (PIC18(L)F1XK22) I/O TABLE 1: Y PGD IOC/INT1 Y PG
PIC18(L)F1XK22 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 6 2.0 Oscillator Module........................................................................................................................................................................ 12 3.0 Memory Organization .....................................................................
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PIC18(L)F1XK22 1.0 DEVICE OVERVIEW This family offers the advantages of all PIC18 microcontrollers – namely, high computational performance with the addition of high-endurance, Flash program memory. On top of these features, the PIC18(L)F1XK22 family introduces design enhancements that make these microcontrollers a logical choice for many high-performance, power sensitive applications. 1.1 1.1.
PIC18(L)F1XK22 1.2 Other Special Features • Memory Endurance: The Flash cells for both program memory and data EEPROM are rated to last for many thousands of erase/write cycles – up to 10K for program memory and 100K for EEPROM. Data retention without refresh is conservatively estimated to be greater than 40 years. • Self-programmability: These devices can write to their own program memory spaces under internal software control.
PIC18(L)F1XK22 TABLE 1-1: DEVICE FEATURES FOR THE PIC18(L)F1XK22 (20-PIN DEVICES) Features Voltage Range (1.8 - 5.5V) Program Memory (Bytes) PIC18F13K22 PIC18LF13K22 PIC18F14K22 PIC18LF14K22 2.3-5.5V 1.8V-3.6V 2.3-5.5V 1.8V-3.
PIC18(L)F1XK22 FIGURE 1-1: PIC18(L)F1XK22 BLOCK DIAGRAM Data Bus<8> Table Pointer<21> Data Latch 8 8 inc/dec logic PCLATU PCLATH 21 PORTA Data Memory (512/768 bytes) Address Latch 20 PCU PCH PCL Program Counter 12 Data Address<12> 31-Level Stack 4 BSR Address Latch STKPTR Program Memory 12 FSR0 FSR1 FSR2 Data Latch 4 Access Bank 12 PORTB 8 inc/dec logic Table Latch RA0 RA1 RA1 RA3 RA4 RA5 RB4 RB5 RB6 RB7 Address Decode ROM Latch Instruction Bus <16> IR Instruction Decode and Cont
PIC18(L)F1XK22 TABLE 1-2: PIC18(L)F1XK22 PIN SUMMARY PDIP/SSOP/ SOIC QFN Pin Number RA0/AN0/CVREF/VREF-/C1IN+/INT0/PGD RA0 AN0 CVREF/DAC1OUT VREFC1IN+ INT0 PGD 19 16 RA1/AN1/C12IN0-/VREF+/INT1/PGC RA1 AN1 C12IN0VREF+ INT1 PGC 18 RA2/AN2/C1OUT/T0CKI/INT2/SRQ RA2 AN2 C1OUT T0CKI INT2 SRQ 17 RA3/MCLR/VPP RA3 MCLR VPP 4 RA4/AN3/OSC2/CLKOUT RA4 AN3 OSC2 3 Pin Type Buffer Type I/O I O I I I I/O TTL Analog Analog Analog Analog ST ST Digital I/O ADC channel 0 DAC reference voltage output ADC and
PIC18(L)F1XK22 TABLE 1-2: PIC18(L)F1XK22 PIN SUMMARY (CONTINUED) PDIP/SSOP/ SOIC QFN Pin Number RB5/AN11/RX/DT RB5 AN11 RX DT 12 9 RB6/SCK/SCL RB6 SCK SCL 11 RB7/TX/CK RB7 TX CK 10 RC0/AN4/C2IN+ RC0 AN4 C2IN+ 16 RC1/AN5/C12INRC1 AN5 C12IN- 15 RC2/AN6/C12IN2-/P1D RC2 AN6 C12IN2P1D 14 RC3/AN7/C12IN3-/P1C/PGM RC3 AN7 C12IN3P1C PGM 7 RC4/C2OUT/P1B/SRNQ RC4 C2OUT P1B SRNQ 6 RC5/CCP1/P1A RC5 CCP1 P1A 5 RC6/AN8/SS RC6 AN8 SS 8 RC7/AN9/SDO RC7 AN9 SDO 9 VSS 20 17 P — VDD 1 18 P
PIC18(L)F1XK22 2.0 OSCILLATOR MODULE 2.3 2.1 Overview The SCS bits of the OSCCON register select between the following clock sources: The oscillator module has a variety of clock sources and features that allow it to be used in a wide range of applications, maximizing performance and minimizing power consumption. Figure 2-1 illustrates a block diagram of the oscillator module.
PIC18(L)F1XK22 FIGURE 2-1: OSC1/T13CKI PIC® MCU CLOCK SOURCE BLOCK DIAGRAM Primary Oscillator, External and Secondary Oscillator PIC18(L)F1XK22 Timer1/Timer3 Sleep OSC2 PCLKEN PRI_SD LP, XT, HS, RC, EC, 1 Secondary Osc. 4 x PLL IDLEN Sleep 0x 0 FOSC<3:0> Peripherals PLL_EN PLLEN Internal Osc.
PIC18(L)F1XK22 2.4.1 PRIMARY EXTERNAL OSCILLATOR SHUTDOWN The Primary External Oscillator can be enabled or disabled via software. To enable software control of the Primary External Oscillator, the PCLKEN bit of the CONFIG1H Configuration register must be set. With the PCLKEN bit set, the Primary External Oscillator is controlled by the PRI_SD bit of the OSCCON2 register. The Primary External Oscillator will be enabled when the PRI_SD bit is set, and disabled when the PRI_SD bit is clear. Note: 2.4.
PIC18(L)F1XK22 FIGURE 2-3: CERAMIC RESONATOR OPERATION (XT OR HS MODE) PIC® MCU OSC1/CLKIN C1 To Internal Logic RP(3) RF(2) C2 Ceramic RS(1) Resonator Sleep OSC2/CLKOUT Note 1: A series resistor (RS) may be required for ceramic resonators with low drive level. 2: The value of RF varies with the Oscillator mode selected (typically between 2 M to 10 M. 3: An additional parallel feedback resistor (RP) may be required for proper ceramic resonator operation. 2.4.
PIC18(L)F1XK22 2.6 Internal Oscillator The internal oscillator module contains two independent oscillators which are: • LFINTOSC: Low-Frequency Internal Oscillator • HFINTOSC: High-Frequency Internal Oscillator When operating with either oscillator, OSC1 will be an I/O and OSC2 will be either an I/O or CLKOUT. The CLKOUT function is selected by the FOSC bits of the CONFIG1H Configuration register.
PIC18(L)F1XK22 2.7 Oscillator Control The Oscillator Control (OSCCON) (Register 2-1) and the Oscillator Control 2 (OSCCON2) (Register 2-2) registers control the system clock and frequency selection options.
PIC18(L)F1XK22 REGISTER 2-2: OSCCON2: OSCILLATOR CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R-x — — — — — PRI_SD HFIOFL LFIOFS bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ q = depends on condition -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-3 Unimplemented: Read as ‘0’ bit 2 PRI_SD: Primary Oscillator Drive Circuit shutdown bit 1 = Oscillator drive circuit on 0 = Oscillator drive circuit o
PIC18(L)F1XK22 2.7.1 OSCTUNE REGISTER The HFINTOSC is factory-calibrated, but can be adjusted in software by writing to the TUN<5:0> bits of the OSCTUNE register (Register 2-3). The default value of the TUN<5:0> is ‘000000’. The value is a 6-bit two’s complement number. When the OSCTUNE register is modified, the HFINTOSC frequency will begin shifting to the new frequency. Code execution continues during this shift, while giving no indication that the shift has occurred.
PIC18(L)F1XK22 2.8 Oscillator Start-up Timer The Primary External Oscillator, when configured for LP, XT or HS modes, incorporates an Oscillator Start-up Timer (OST). The OST ensures that the oscillator starts and provides a stable clock to the oscillator module. The OST times out when 1024 oscillations on OSC1 have occurred. During the OST period, with the system clock set to the Primary External Oscillator, the program counter does not increment suspending program execution.
PIC18(L)F1XK22 TABLE 2-2: EXAMPLES OF DELAYS DUE TO CLOCK SWITCHING Switch From Switch To Oscillator Delay Sleep/POR LFINTOSC HFINTOSC Oscillator Warm-up Delay (TWARM) Sleep/POR LP, XT, HS 1024 clock cycles Sleep/POR EC, RC 8 Clock Cycles 2.10 4x Phase Lock Loop Frequency Multiplier A Phase Locked Loop (PLL) circuit is provided as an option for users who wish to use a lower-frequency external oscillator or to operate at 32 MHz or 64 MHz with the HFINTOSC.
PIC18(L)F1XK22 2.12 2.12.3 Fail-Safe Clock Monitor The Fail-Safe Clock Monitor (FSCM) allows the device to continue operating should the external oscillator fail. The FSCM can detect oscillator failure any time after the Oscillator Start-up Timer (OST) has expired. The FSCM is enabled by setting the FCMEN bit in the CONFIG1H Configuration register. The FSCM is applicable to all external oscillator modes (LP, XT, HS, EC and RC).
PIC18(L)F1XK22 FIGURE 2-7: FSCM TIMING DIAGRAM Sample Clock Oscillator Failure System Clock Output Clock Monitor Output (Q) Failure Detected OSCFIF Test Note: TABLE 2-5: Name CONFIG1H Test Test The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in this example have been chosen for clarity.
PIC18(L)F1XK22 3.0 MEMORY ORGANIZATION 3.1 There are three types of memory in PIC18 Enhanced microcontroller devices: • Program Memory • Data RAM • Data EEPROM Program Memory Organization PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte Program Memory (PC) space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction).
PIC18(L)F1XK22 3.1.1 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21-bit wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC<15:8> bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU.
PIC18(L)F1XK22 3.1.2.2 Return Stack Pointer (STKPTR) When the stack has been popped enough times to unload the stack, the next pop will return a value of zero to the PC and sets the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. The STKPTR register (Figure 3-1) contains the Stack Pointer value, the STKFUL (Stack Full) bit and the STKUNF (Stack Underflow) bits. The value of the Stack Pointer can be 0 through 31.
PIC18(L)F1XK22 3.1.2.4 Stack Overflow and Underflow Resets Device Resets on Stack Overflow and Stack Underflow conditions are enabled by setting the STVREN bit in Configuration Register 4L. When STVREN is set, a full or underflow will set the appropriate STKOVF or STKUNF bit and then cause a device Reset. When STVREN is cleared, a full or underflow condition will set the appropriate STKOVF or STKUNF bit but not cause a device Reset.
PIC18(L)F1XK22 3.2 3.2.2 PIC18 Instruction Cycle 3.2.1 An “Instruction Cycle” consists of four Q cycles: Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the program counter to change (e.g.
PIC18(L)F1XK22 3.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as either two bytes or four bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSb = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSb will always read ‘0’ (see Section 3.1.1 “Program Counter”).
PIC18(L)F1XK22 3.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 3.5 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each.
PIC18(L)F1XK22 FIGURE 3-5: DATA MEMORY MAP FOR PIC18(L)F13K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 00h Access RAM FFh 00h GPR Bank 0 000h 05Fh 060h 0FFh 100h Bank 1 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 FFh 00h 1FFh 200h FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h Unused Read 00h 8FFh 900h FFh 00h 9FFh A00h FFh 00h
PIC18(L)F1XK22 FIGURE 3-6: DATA MEMORY MAP FOR PIC18(L)F14K22 DEVICES BSR<3:0> = 0000 = 0001 = 0010 = 0011 = 0100 = 0101 = 0110 = 0111 = 1000 = 1001 = 1010 = 1011 = 1100 = 1101 = 1110 00h Access RAM FFh 00h GPR Bank 0 Bank 2 Bank 3 Bank 4 Bank 5 Bank 6 Bank 7 Bank 8 Bank 9 000h 05Fh 060h 0FFh 100h GPR Bank 1 FFh 00h 1FFh 200h FFh 00h 2FFh 300h FFh 00h 3FFh 400h FFh 00h 4FFh 500h FFh 00h 5FFh 600h FFh 00h 6FFh 700h FFh 00h Unused Read 00h 9FFh A00h FFh 00h AFFh B
PIC18(L)F1XK22 FIGURE 3-7: USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) 0 Data Memory BSR(1) 7 0 0 0 0 0 0 1 000h Bank 0 0 100h Bank Select(2) 200h Bank 1 Bank 2 300h 00h 7 FFh 00h 1 From Opcode(2) 1 1 1 1 1 0 1 1 FFh 00h FFh 00h Bank 3 through Bank 13 E00h F00h FFFh Note 1: 2: Bank 14 Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR<3:0>) to the registers of the Access Bank.
PIC18(L)F1XK22 3.3.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from or written to the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient.
PIC18(L)F1XK22 TABLE 3-1: Address FFFh SPECIAL FUNCTION REGISTER MAP FOR PIC18(L)F1XK22 DEVICES Name Address TOSU FD7h Name TMR0H Address FAFh Name Address SPBRG Name Address Name F87h — (2) F5Fh —(2) F5Eh —(2) FFEh TOSH FD6h TMR0L FAEh RCREG F86h —(2) FFDh TOSL FD5h T0CON FADh TXREG F85h —(2) F5Dh —(2) F84h — (2) F5Ch —(2) F83h —(2) F5Bh —(2) F82h PORTC F5Ah —(2) FFCh FFBh STKPTR FD4h PCLATU FD3h (2) — OSCCON FACh FABh TXSTA RCSTA (2) FFAh PCLAT
PIC18(L)F1XK22 TABLE 3-2: File Name TOSU REGISTER FILE SUMMARY (PIC18(L)F1XK22) Bit 7 Bit 6 Bit 5 — — — TOSH Top-of-Stack, High Byte (TOS<15:8>) TOSL Top-of-Stack, Low Byte (TOS<7:0>) STKPTR PCLATU STKOVF STKUNF — — — — PCLATH Holding Register for PC<15:8> PCL PC, Low Byte (PC<7:0>) TBLPTRU — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Top-of-Stack Upper Byte (TOS<20:16>) Value on POR, BOR Details on page: ---0 0000 245, 25 0000 0000 245, 25 0000 0000 245, 25 SP4 SP3 SP2 SP1 SP0 Hold
PIC18(L)F1XK22 TABLE 3-2: File Name REGISTER FILE SUMMARY (PIC18(L)F1XK22) (CONTINUED) Bit 7 Bit 6 TMR0H Timer0 Register, High Byte TMR0L Timer0 Register, Low Byte T0CON Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: 0000 0000 246, 92 xxxx xxxx 246, 92 TMR0ON T08BIT T0CS T0SE PSA T0PS2 T0PS1 T0PS0 OSCCON IDLEN IRCF2 IRCF1 IRCF0 OSTS HFIOFS SCS1 SCS0 0011 qq00 246, 17 OSCCON2 — — — — — PRI_SD HFIOFL LFIOFS ---- -10x 246, 18 WDTCON — — —
PIC18(L)F1XK22 TABLE 3-2: File Name REGISTER FILE SUMMARY (PIC18(L)F1XK22) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: SPBRGH EUSART Baud Rate Generator Register, High Byte 0000 0000 247, 182 SPBRG EUSART Baud Rate Generator Register, Low Byte 0000 0000 247, 182 RCREG EUSART Receive Register 0000 0000 247, 175 TXREG EUSART Transmit Register 0000 0000 247, 172 TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 247, 179 R
PIC18(L)F1XK22 3.3.5 STATUS REGISTER The STATUS register, shown in Register 3-2, contains the arithmetic status of the ALU. As with any other SFR, it can be the operand for any instruction. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, the results of the instruction are not written; instead, the STATUS register is updated according to the instruction performed.
PIC18(L)F1XK22 3.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 3.5 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – through the program counter – information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed.
PIC18(L)F1XK22 3.4.3.1 FSR Registers and the INDF Operand 3.4.3.2 At the core of indirect addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. Each FSR pair holds a 12-bit value, therefore the four upper bits of the FSRnH register are not used. The 12-bit FSR value can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations.
PIC18(L)F1XK22 Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of indexed addressing in the data memory space.
PIC18(L)F1XK22 FIGURE 3-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When ‘a’ = 0 and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and 0FFh. This is the same as locations F60h to FFFh (Bank 15) of data memory. Locations below 60h are not available in this addressing mode.
PIC18(L)F1XK22 3.5.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the first 96 locations of Access RAM (00h to 5Fh) are mapped. Rather than containing just the contents of the bottom section of Bank 0, this mode maps the contents from a user defined “window” that can be located anywhere in the data memory space.
PIC18(L)F1XK22 4.0 FLASH PROGRAM MEMORY 4.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: A read from program memory is executed one byte at a time.
PIC18(L)F1XK22 FIGURE 4-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Table Pointer(1) TBLPTRU TBLPTRH Holding Registers Table Latch (8-bit) TBLPTRL TABLAT Program Memory (TBLPTR) Note 1: During table writes the Table Pointer does not point directly to Program Memory. The LSBs of TBLPRTL actually point to an address within the write block holding registers. The MSBs of the Table Pointer determine where the write block will eventually be written.
PIC18(L)F1XK22 REGISTER 4-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory
PIC18(L)F1XK22 4.2.2 TABLAT – TABLE LATCH REGISTER 4.2.4 The Table Latch (TABLAT) is an 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 4.2.3 TABLE POINTER BOUNDARIES TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory directly into the TABLAT register.
PIC18(L)F1XK22 4.3 Reading the Flash Program Memory The TBLRD instruction retrieves data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. The internal program memory is typically organized by words. The Least Significant bit of the address selects between the high and low bytes of the word. Figure 4-4 shows the interface between the internal program memory and the TABLAT. TBLPTR points to a byte address in program space.
PIC18(L)F1XK22 4.4 Erasing Flash Program Memory The minimum erase block is 32 words or 64 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the Microcontroller itself, a block of 64 bytes of program memory is erased. The Most Significant 16 bits of the TBLPTR<21:6> point to the block being erased. The TBLPTR<5:0> bits are ignored.
PIC18(L)F1XK22 4.5 Writing to Flash Program Memory The programming block size is 8 or 16 bytes, depending on the device (See Table 4-1). Word or byte programming is not supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are only as many holding registers as there are bytes in a write block (See Table 4-1).
PIC18(L)F1XK22 EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF D'64’ COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; number of bytes in erase block TBLRD*+ MOVF MOVWF DECFSZ BRA TABLAT, W POSTINC0 COUNTER READ_BLOCK MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L NEW_DATA_LOW POSTINC0 NEW_DATA_HIGH INDF0 ; point
PIC18(L)F1XK22 EXAMPLE 4-3: WRITING TO FLASH PROGRAM MEMORY (CONTINUED) DECFSZ BRA COUNTER WRITE_WORD_TO_HREGS ; loop until holding registers are full BSF BCF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF DCFSZ BRA BSF BCF EECON1, EEPGD EECON1, CFGS EECON1, WREN INTCON, GIE 55h EECON2 0AAh EECON2 EECON1, WR COUNTER2 WRITE_BYTE_TO_HREGS INTCON, GIE EECON1, WREN ; ; ; ; PROGRAM_MEMORY Required Sequence 4.5.
PIC18(L)F1XK22 5.0 DATA EEPROM MEMORY The data EEPROM is a nonvolatile memory array, separate from the data RAM and program memory, which is used for long-term storage of program data. It is not directly mapped in either the register file or program memory space but is indirectly addressed through the Special Function Registers (SFRs). The EEPROM is readable and writable during normal operation over the entire VDD range.
PIC18(L)F1XK22 REGISTER 5-1: EECON1: DATA EEPROM CONTROL 1 REGISTER R/W-x R/W-x U-0 R/W-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD CFGS — FREE WRERR WREN WR RD bit 7 bit 0 Legend: R = Readable bit W = Writable bit S = Bit can be set by software, but not cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘0’ = Bit is cleared ‘1’ = Bit is set x = Bit is unknown bit 7 EEPGD: Flash Program or Data EEPROM Memory Select bit 1 = Access Flash program memory 0 = Access data EEPROM memory
PIC18(L)F1XK22 5.3 Reading the Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit of the EECON1 register and then set control bit, RD. The data is available on the very next instruction cycle; therefore, the EEDATA register can be read by the next instruction. EEDATA will hold this value until another read operation, or until it is written to by the user (during a write operation). The basic process is shown in Example 5-1.
PIC18(L)F1XK22 5.6 Operation During Code-Protect 5.8 Data EEPROM memory has its own code-protect bits in Configuration Words. External read and write operations are disabled if code protection is enabled. The microcontroller itself can both read and write to the internal data EEPROM, regardless of the state of the code-protect Configuration bit. Refer to Section 23.0 “Special Features of the CPU” for additional information. 5.
PIC18(L)F1XK22 6.0 8 x 8 HARDWARE MULTIPLIER 6.1 Introduction EXAMPLE 6-1: MOVF MULWF All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register.
PIC18(L)F1XK22 Example 6-3 shows the sequence to do a 16 x 16 unsigned multiplication. Equation 6-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES<3:0>).
PIC18(L)F1XK22 7.0 INTERRUPTS The PIC18(L)F1XK22 devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h. A high priority interrupt event will interrupt a low priority interrupt that may be in progress. There are twelve registers which are used to control interrupt operation.
PIC18(L)F1XK22 Note: Do not use the MOVFF instruction to modify any of the interrupt control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior.
PIC18(L)F1XK22 7.4 INTCON Registers The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. Note: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling.
PIC18(L)F1XK22 REGISTER 7-2: INTCON2: INTERRUPT CONTROL 2 REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 R/W-1 RABPU INTEDG0 INTEDG1 INTEDG2 — TMR0IP — RABIP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 RABPU: PORTA and PORTB Pull-up Enable bit 1 = PORTA and PORTB pull-ups are disabled 0 = PORTA and PORTB pull-ups are enabled provided that the pin is an inp
PIC18(L)F1XK22 REGISTER 7-3: INTCON3: INTERRUPT CONTROL 3 REGISTER R/W-1 R/W-1 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 INT2IP INT1IP — INT2IE INT1IE — INT2IF INT1IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Lo
PIC18(L)F1XK22 7.5 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Request Flag registers (PIR1 and PIR2). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE of the INTCON register.
PIC18(L)F1XK22 REGISTER 7-5: PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = Device oscillator failed, clock input has changed to HFINTOSC (must be cleared by software) 0 = Device
PIC18(L)F1XK22 7.6 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Enable registers (PIE1 and PIE2). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts.
PIC18(L)F1XK22 REGISTER 7-7: PIE2: PERIPHERAL INTERRUPT ENABLE (FLAG) REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 C1IE: Comparator C1 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5 C2IE: Comparator C
PIC18(L)F1XK22 7.7 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are two Peripheral Interrupt Priority registers (IPR1 and IPR2). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set.
PIC18(L)F1XK22 REGISTER 7-9: IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 U-0 R/W-1 U-0 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 C1IP: Comparator C1 Interrupt Priority bit 1 = High priority 0 = Low priority bit 5
PIC18(L)F1XK22 7.8 RCON Register The RCON register contains flag bits which are used to determine the cause of the last Reset or wake-up from Idle or Sleep modes. RCON also contains the IPEN bit which enables interrupt priorities. The operation of the SBOREN bit and the Reset flag bits is discussed in more detail in Section 22.1 “RCON Register”.
PIC18(L)F1XK22 7.9 INTx Pin Interrupts 7.10 External interrupts on the INT0, INT1 and INT2 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit, INTxF, is set. This interrupt can be disabled by clearing the corresponding enable bit, INTxE.
PIC18(L)F1XK22 8.0 I/O PORTS 8.1 There are up to three ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation.
PIC18(L)F1XK22 This interrupt can wake the device from the Sleep mode, or any of the Idle modes. The user, in the Interrupt Service Routine, can clear the interrupt in the following manner: a) b) Any read or write of PORTA to clear the mismatch condition (except when PORTA is the source or destination of a MOVFF instruction). Clear the flag bit, RABIF. A mismatch condition will continue to set the RABIF flag bit.
PIC18(L)F1XK22 REGISTER 8-1: PORTA: PORTA REGISTER U-0 U-0 R/W-x R/W-x R-x R/W-x R/W-x R/W-x — — RA5 RA4 RA3 RA2 RA1 RA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 RA<5:0>: PORTA I/O Pin bit(1) 1 = Port pin is > VIH 0 = Port pin is < VIL Note 1: x = Bit is unknown The RA3 bit is only available when Master Clear Reset is disabled (MCL
PIC18(L)F1XK22 REGISTER 8-3: LATA: PORTA DATA LATCH REGISTER U-0 U-0 R/W-x R/W-x U-0 R/W-x R/W-x R/W-x — — LATA5 LATA4 — LATA2 LATA1 LATA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 LATA<5:4>: RA<5:4> Port I/O Output Latch Register bits bit 3 Unimplemented: Read as ‘0’ bit 2-0 LATA<2:0>: RA<2:0> Port I/O Output Latch Register bits
PIC18(L)F1XK22 TABLE 8-1: Pin RA0/AN0/CVREF/ DAC1OUT/VREF-/ C1IN+/INT0/PGD PORTA I/O SUMMARY Function TRIS Setting I/O I/O Type RA0 0 O DIG RA2/AN2/C1OUT/ T0CKI/INT2/SRQ RA3/MCLR/VPP RA4/AN3/OSC2/ CLKOUT RA5/OSC1/CLKIN/ T13CKI Legend: Note 1: LATA<0> data output. 1 I TTL PORTA<0> data input; Programmable weak pull-up. AN0 1 I ANA ADC channel 0 input. CVREF/ DAC1OUT x O ANA DAC reference voltage output. VREF- 1 I ANA ADC and DAC reference voltage (low) input.
PIC18(L)F1XK22 TABLE 8-2: Name ANSEL INTCON INTCON2 SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 Bit 6 ANS7 ANS6 GIE/GIEH PEIE/GIEL RABPU INTEDG0 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 247 TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 244 — TMR0IP — RABIP 244 IOCA2 IOCA1 IOCA0 247 LATA2 LATA1 LATA0 247 INTEDG1 INTEDG2 (2) IOCA — — IOCA5 IOCA4 LATA — — LATA5(1) LATA4(1) — PORTA — — RA5(1) RA4(1) RA3(2) R
PIC18(L)F1XK22 8.2 PORTB, TRISB and LATB Registers PORTB is an 4-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., disable the output driver). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). A mismatch condition will continue to set the RABIF flag bit.
PIC18(L)F1XK22 REGISTER 8-6: PORTB: PORTB REGISTER R/W-x R/W-x R/W-x R/W-x U-0 U-0 U-0 U-0 RB7 RB6 RB5 RB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 RB<7:4>: PORTB I/O Pin bit 1 = Port pin is >VIH 0 = Port pin is
PIC18(L)F1XK22 REGISTER 8-9: WPUB: WEAK PULL-UP PORTB REGISTER R/W-1 R/W-1 R/W-1 R/W-1 U-0 U-0 U-0 U-0 WPUB7 WPUB6 WPUB5 WPUB4 — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 WPUB<7:4>: Weak Pull-up Enable bit 1 = Pull-up enabled 0 = Pull-up disabled bit 3-0 Unimplemented: Read as ‘0’ REGISTER 8-10: x = Bit is unknown IOCB: INTERRUPT-ON-CHANGE PORTB REGISTER R/W-0
PIC18(L)F1XK22 TABLE 8-3: Pin PORTB I/O SUMMARY Function TRIS Setting I/O I/O Type RB4 0 O DIG RB4/AN10/SDI/ SDA RB5/AN11/RX/DT RB6/SCK/SCL 1 I TTL PORTB<4> data input; Programmable weak pull-up. 1 I ANA ADC input channel 10. SDI 1 I ST SPI data input (MSSP module). SDA 1 O DIG I2C data output (MSSP module). 1 I I2C I2C data input (MSSP module); input type depends on module setting. 0 O DIG LATB<5> data output. 1 I TTL PORTB<5> data input; Programmable weak pull-up.
PIC18(L)F1XK22 TABLE 8-4: Name ANSELH INTCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 Bit 6 — — GIE/GIEH PEIE/GIEL Bit 5 Bit 3 — — ANS11 ANS10 ANS9 ANS8 247 TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 244 — TMR0IP — RABIP 244 — — — — 247 247 INTEDG0 INTEDG1 INTEDG2 Bit 2 Bit 1 Bit 0 Reset Values on page Bit 4 INTCON2 RABPU IOCB IOCB7 IOCB6 IOCB5 IOCB4 LATB LATB7 LATB6 LATB5 LATB4 PORTB RB7 RB6 RB5 RB4 — — — — RCSTA SPEN RX9 SREN CREN ADDEN
PIC18(L)F1XK22 8.3 All the pins on PORTC are implemented with Schmitt Trigger input buffer. Each pin is individually configurable as an input or output. PORTC, TRISC and LATC Registers PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., disable the output driver). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e.
PIC18(L)F1XK22 REGISTER 8-13: LATC: PORTC DATA LATCH REGISTER R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x LATC7 LATC6 LATC5 LATC4 LATC3 LATC2 LATC1 LATC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown LATC<7:0>: RB<7:0> Port I/O Output Latch Register bits 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 TABLE 8-5: Pin RC0/AN4/C2IN+ RC1/AN5/ C12IN1- RC2/AN6/ C12IN2-/P1D RC3/AN7/ C12IN3-/P1C/ PGM RC4/C2OUT/P1B/ SRNQ PORTC I/O SUMMARY Function TRIS Setting I/O I/O Type RC0 0 O DIG 1 I ST AN4 1 I ANA A/D input channel 4. C2IN+ 1 I ANA Comparators C2 noninverting input. RC1 0 O DIG LATC<1> data output. 1 I ST AN5 1 I ANA A/D input channel 5. C12IN1- 1 I ANA Comparators C1 and C2 inverting input, channel 1. RC2 0 O DIG LATC<2> data output.
PIC18(L)F1XK22 TABLE 8-6: Name ANSEL ANSELH CCP1CON SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 247 — — — — ANS11 ANS10 ANS9 ANS8 247 P1M1 P1M0 DC1B1 DC1B0 CCP1M3 CCP1M2 CCP1M1 CCP1M0 ECCP1AS ECCPASE ECCPAS2 ECCPAS1 ECCPAS0 PSSAC1 PSSAC0 PSSBD1 INTCON GIE/GIEH PEIE/GIEL 246 PSSBD0 246 TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 244 INTEDG1 INTEDG2 — TMR0IP
PIC18(L)F1XK22 8.4 Port Analog Control Some port pins are multiplexed with analog functions such as the Analog-to-Digital Converter and comparators. When these I/O pins are to be used as analog inputs it is necessary to disable the digital input buffer to avoid excessive current caused by improper biasing of the digital input. Individual control of the digital input buffers on pins which share analog functions is provided by the ANSEL and ANSELH REGISTER 8-14: registers.
PIC18(L)F1XK22 REGISTER 8-15: ANSELH: ANALOG SELECT HIGH REGISTER U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 — — — — ANS11 ANS10 ANS9 ANS8 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-4 Unimplemented: Read as ‘0’ bit 3 ANS11: RB5 Analog Select Control bit 1 = Digital input buffer of RB5 is disabled 0 = Digital input buffer of RB5 is enabled bit 2 ANS10: RB4 Analog Select Cont
PIC18(L)F1XK22 8.5 Port Slew Rate Control The output slew rate of each port is programmable to select either the standard transition rate or a reduced transition rate of 0.1 times the standard to minimize EMI. The reduced transition time is the default slew rate for all ports.
PIC18(L)F1XK22 9.0 The T0CON register (Register 9-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable.
PIC18(L)F1XK22 9.1 Timer0 Operation 9.2 Timer0 can operate as either a timer or a counter; the mode is selected with the T0CS bit of the T0CON register. In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 9.3 “Prescaler”). Timer0 incrementing is inhibited for two instruction cycles following a TMR0 register write.
PIC18(L)F1XK22 FIGURE 9-2: TIMER0 BLOCK DIAGRAM (16-BIT MODE) FOSC/4 0 1 Sync with Internal Clocks 1 Programmable Prescaler T0CKI pin T0SE T0CS 0 TMR0 High Byte TMR0L 8 Set TMR0IF on Overflow (2 TCY Delay) 3 Read TMR0L T0PS<2:0> Write TMR0L PSA 8 8 TMR0H 8 8 Internal Data Bus Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI. TMR0 Prescaler is set to maximum (1:256), but on Reset is not assigned to the timer. Note: 9.3 9.3.
PIC18(L)F1XK22 10.0 TIMER1 MODULE The Timer1 timer/counter module incorporates the following features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable internal or external clock source and Timer1 oscillator options • Interrupt-on-overflow • Reset on CCP Special Event Trigger • Device clock status flag (T1RUN) REGISTER 10-1: A simplified block diagram of the Timer1 module is shown in Figure 10-1.
PIC18(L)F1XK22 10.1 Timer1 Operation Timer1 can operate in one of the following modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS of the T1CON register. When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer1 increments on every rising edge of either the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18(L)F1XK22 FIGURE 10-2: TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Clock Input Timer1 Oscillator 1 OSC1/T13CKI 1 FOSC/4 Internal Clock OSC2 Synchronize Prescaler 1, 2, 4, 8 0 Detect 0 2 INTOSC Without CLKOUT Sleep Input TMR1CS T1OSCEN(1) Timer1 On/Off T1CKPS<1:0> T1SYNC TMR1ON Clear TMR1 (CCP Special Event Trigger) TMR1 High Byte TMR1L 8 Set TMR1IF on Overflow Read TMR1L Write TMR1L 8 8 TMR1H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN, is cleared, the invert
PIC18(L)F1XK22 10.2 Timer1 16-Bit Read/Write Mode Timer1 can be configured for 16-bit reads and writes (see Figure 10-2). When the RD16 control bit of the T1CON register is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L will load the contents of the high byte of Timer1 into the Timer1 high byte buffer.
PIC18(L)F1XK22 TABLE 10-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Osc Type Freq. C1 C2 LP 32 kHz 27 pF(1) 27 pF(1) Note 1: Microchip suggests these values only as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components.
PIC18(L)F1XK22 EXAMPLE 10-1: IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE RTCinit MOVLW MOVWF CLRF MOVLW MOVWF CLRF CLRF MOVLW MOVWF BSF RETURN 80h TMR1H TMR1L b’00001111’ T1CON secs mins .12 hours PIE1, TMR1IE BSF BCF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF INCF MOVLW CPFSGT RETURN CLRF RETURN TMR1H, 7 PIR1, TMR1IF secs, F .
PIC18(L)F1XK22 11.0 TIMER2 MODULE 11.
PIC18(L)F1XK22 11.2 Timer2 Interrupt 11.3 Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2-to-PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF of the PIR1 register. The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE of the PIE1 register.
PIC18(L)F1XK22 12.0 TIMER3 MODULE The Timer3 module timer/counter incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR3H and TMR3L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on CCP Special Event Trigger REGISTER 12-1: A simplified block diagram of the Timer3 module is shown in Figure 12-1.
PIC18(L)F1XK22 12.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR3CS of the T3CON register. When TMR3CS is cleared (= 0), Timer3 increments on every internal instruction cycle (FOSC/4). When the bit is set, Timer3 increments on every rising edge of the Timer1 external clock input or the Timer1 oscillator, if enabled.
PIC18(L)F1XK22 FIGURE 12-2: TIMER3 BLOCK DIAGRAM (16-BIT READ/WRITE MODE) Timer1 Clock Input Timer1 Oscillator 1 OSC1/T1OSI 1 FOSC/4 Internal Clock OSC2 Synchronize Prescaler 1, 2, 4, 8 Detect 0 0 2 INTOSC Without CLKOUT Sleep Input TMR3CS Timer3 On/Off T1OSCEN(1) T3CKPS<1:0> T3SYNC TMR3ON CCP1 Special Event Trigger CCP1 Select from T3CON<3> Clear TMR3 Set TMR3IF on Overflow TMR3 High Byte TMR3L 8 Read TMR1L Write TMR1L 8 8 TMR3H 8 8 Internal Data Bus Note 1: When enable bit, T1OSCEN
PIC18(L)F1XK22 12.2 Timer3 16-Bit Read/Write Mode 12.4 Timer3 Interrupt Timer3 can be configured for 16-bit reads and writes (see Figure 12-2). When the RD16 control bit of the T3CON register is set, the address for TMR3H is mapped to a buffer register for the high byte of Timer3. A read from TMR3L will load the contents of the high byte of Timer3 into the Timer3 High Byte Buffer register.
PIC18(L)F1XK22 13.0 CCP1 is implemented as a standard CCP module with enhanced PWM capabilities. These include: ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE PIC18(L)F1XK22 devices have one ECCP (Capture/Compare/PWM) module. The module contains a 16-bit register which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register.
PIC18(L)F1XK22 In addition to the expanded range of modes available through the CCP1CON register and ECCP1AS register, the ECCP module has two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • PWM1CON (Dead-band delay) • PSTRCON (Output steering) 13.1 ECCP Outputs and Configuration The enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode.
PIC18(L)F1XK22 13.2.4 CCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCP1M<3:0>). Whenever the CCP module is turned off or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt.
PIC18(L)F1XK22 13.3 13.3.2 Compare Mode TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPR1 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP1 pin can be: Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. • • • • 13.3.
PIC18(L)F1XK22 13.4 The PWM outputs are multiplexed with I/O pins and are designated P1A, P1B, P1C and P1D. The polarity of the PWM pins is configurable and is selected by setting the CCP1M bits in the CCP1CON register appropriately. PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10-bits of resolution. It can do this through four different PWM output modes: • • • • Table 13-1 shows the pin assignments for each Enhanced PWM mode.
PIC18(L)F1XK22 FIGURE 13-4: EXAMPLE PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) P1M<1:0> Signal PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated Delay(1) Delay(1) P1A Modulated 10 (Half-Bridge) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<
PIC18(L)F1XK22 FIGURE 13-5: EXAMPLE ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) Signal P1M<1:0> PR2+1 Pulse Width 0 Period 00 (Single Output) P1A Modulated P1A Modulated 10 (Half-Bridge) Delay(1) Delay(1) P1B Modulated P1A Active 01 (Full-Bridge, Forward) P1B Inactive P1C Inactive P1D Modulated P1A Inactive 11 (Full-Bridge, Reverse) P1B Modulated P1C Active P1D Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPR1L<7:0>:CCP
PIC18(L)F1XK22 13.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the CCP1/P1A pin, while the complementary PWM output signal is output on the P1B pin (see Figure 13-6). This mode can be used for half-bridge applications, as shown in Figure 13-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals.
PIC18(L)F1XK22 13.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of Full-Bridge application is shown in Figure 13-8. In the Forward mode, pin CCP1/P1A is driven to its active state, pin P1D is modulated, while P1B and P1C will be driven to their inactive state as shown in Figure 13-9. In the Reverse mode, P1C is driven to its active state, pin P1B is modulated, while P1A and P1D will be driven to their inactive state as shown Figure 13-9.
PIC18(L)F1XK22 FIGURE 13-9: EXAMPLE OF FULL-BRIDGE PWM OUTPUT Forward Mode Period P1A (2) Pulse Width P1B(2) P1C(2) P1D(2) (1) (1) Reverse Mode Period Pulse Width P1A(2) P1B(2) P1C(2) P1D(2) (1) Note 1: 2: (1) At this time, the TMR2 register is equal to the PR2 register. Output signal is shown as active-high. 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 13.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the P1M1 bit in the CCP1CON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the P1M1 bit of the CCP1CON register.
PIC18(L)F1XK22 FIGURE 13-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period P1A P1B PW P1C P1D PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current Note 1: 13.4.3 All signals are shown as active-high. 2: TON is the turn on delay of power switch QC and its driver. 3: TOFF is the turn off delay of power switch QD and its driver.
PIC18(L)F1XK22 13.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE When a shutdown event occurs, two things happen: The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPAS<2:0> bits of the ECCPAS register.
PIC18(L)F1XK22 Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart) the PWM signal will always restart at the beginning of the next PWM period.
PIC18(L)F1XK22 13.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PRSEN bit in the PWM1CON register. If auto-restart is enabled, the ECCPASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPASE bit will be cleared via hardware and normal operation will resume.
PIC18(L)F1XK22 13.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 13-14: In half-bridge applications where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on, and the other turned off), both switches may be on for a short period of time until one switch completely turns off.
PIC18(L)F1XK22 REGISTER 13-3: PWM1CON: ENHANCED PWM CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PRSEN PDC6 PDC5 PDC4 PDC3 PDC2 PDC1 PDC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 PRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically
PIC18(L)F1XK22 13.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can be simultaneously available on multiple pins. Once the Single Output mode is selected (CCP1M<3:2> = 11 and P1M<1:0> = 00 of the CCP1CON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR bits of the PSTRCON register, as shown in Table 13-2.
PIC18(L)F1XK22 FIGURE 13-16: SIMPLIFIED STEERING BLOCK DIAGRAM STRA P1A Signal CCP1M1 1 PORT Data 0 P1A pin STRB CCP1M0 1 PORT Data 0 STRC CCP1M1 1 PORT Data 0 PORT Data P1B pin TRIS P1C pin TRIS STRD CCP1M0 TRIS P1D pin 1 0 TRIS Note 1: Port outputs are configured as shown when the CCP1CON register bits P1M<1:0> = 00 and CCP1M<3:2> = 11. 2: Single PWM output requires setting at least one of the STRx bits. DS40001365F-page 124 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 13.4.7.1 Steering Synchronization The STRSYNC bit of the PSTRCON register gives the user two selections of when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRCON register. In this case, the output signal at the P1 pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin.
PIC18(L)F1XK22 13.4.8 OPERATION IN POWER-MANAGED MODES 13.4.8.1 Operation with Fail-Safe Clock Monitor In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCP pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be stable immediately.
PIC18(L)F1XK22 14.0 14.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC18(L)F1XK22 14.2.1 REGISTERS SSPSR is the shift register used for shifting data in and out. SSPBUF provides indirect access to the SSPSR register. SSPBUF is the buffer register to which data bytes are written, and from which data bytes are read. The MSSP module has four registers for SPI mode operation.
PIC18(L)F1XK22 REGISTER 14-2: SSPCON1: MSSP CONTROL 1 REGISTER (SPI MODE) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word (must be
PIC18(L)F1XK22 14.2.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON1<5:0> and SSPSTAT<7:6>).
PIC18(L)F1XK22 14.2.3 ENABLING SPI I/O 14.2.4 To enable the serial port, SSP Enable bit, SSPEN of the SSPCON1 register, must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, reinitialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins.
PIC18(L)F1XK22 14.2.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 14-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC18(L)F1XK22 14.2.6 SLAVE MODE 14.2.7 In Slave mode, the data is transmitted and received as external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. Before enabling the module in SPI Slave mode, the clock line must match the proper Idle state. The clock line can be observed by reading the SCK pin. The Idle state is determined by the CKP bit of the SSPCON1 register.
PIC18(L)F1XK22 FIGURE 14-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag SSPSR to SSPBUF FIGURE 14-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0
PIC18(L)F1XK22 14.2.8 OPERATION IN POWER-MANAGED MODES Transmit/Receive Shift register. When all eight bits have been received, the MSSP interrupt flag bit will be set and if enabled, will wake the device. In SPI Master mode, module clocks may be operating at a different speed than when in Full Power mode; in the case of the Sleep mode, all clocks are halted. 14.2.9 In all Idle modes, a clock is provided to the peripherals.
PIC18(L)F1XK22 14.3 I2C Mode 14.3.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications as well as 7-bit and 10-bit addressing.
PIC18(L)F1XK22 REGISTER 14-3: R/W-0 SSPSTAT: MSSP STATUS REGISTER (I2C MODE) R/W-0 SMP CKE R-0 R-0 R-0 D/A (1) (1) P S R-0 R/W (2, 3) R-0 R-0 UA BF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard Speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for High-
PIC18(L)F1XK22 SSPCON1: MSSP CONTROL 1 REGISTER (I2C MODE) REGISTER 14-4: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid f
PIC18(L)F1XK22 REGISTER 14-5: R/W-0 GCEN SSPCON2: MSSP CONTROL REGISTER (I2C MODE) R/W-0 R/W-0 ACKSTAT ACKDT(2) R/W-0 (1) ACKEN R/W-0 (1) RCEN R/W-0 (1) PEN R/W-0 (1) RSEN R/W-0 SEN(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Generate interrupt when a general call address 0x00 or 00h is received in the SSP
PIC18(L)F1XK22 14.3.2 OPERATION The MSSP module functions are enabled by setting SSPEN bit of the SSPCON1 register. The SSPCON1 register allows control of the I 2C operation.
PIC18(L)F1XK22 14.3.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the no Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF bit of the SSPSTAT register is set, or bit SSPOV bit of the SSPCON1 register is set.
DS40001365F-page 142 CKP 2 A6 3 A5 4 A4 5 A3 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared by software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
2009-2016 Microchip Technology Inc.
DS40001365F-page 144 2 1 4 1 5 0 7 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 Cleared by software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A1 Cleared
2009-2016 Microchip Technology Inc. CKP UA BF SSPIF 1 SCL S 1 2 1 4 1 5 0 6 7 A9 A8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 3 1 8 9 ACK R/W = 0 1 3 4 5 Cleared in software 2 7 UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address.
PIC18(L)F1XK22 14.3.3.4 SSP Mask Register This register must be initiated prior to setting SSPM<3:0> bits to select the I2C Slave mode (7-bit or 10-bit address). 2 An SSP Mask (SSPMSK) register is available in I C Slave mode as a mask for the value held in the SSPSR register during an address comparison operation. A zero (‘0’) bit in the SSPMSK register has the effect of making the corresponding bit in the SSPSR register a “don’t care”.
PIC18(L)F1XK22 SSPADD: MSSP ADDRESS AND BAUD RATE REGISTER (I2C MODE) REGISTER 14-7: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADD7 ADD6 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown Master mode: bit 7-0 ADD<7:0>: Baud Rate Clock Divider bits SCL pin clock period = ((ADD<7:0> + 1) *4)/FOSC 10-Bit Slave mode — Most Significant Ad
PIC18(L)F1XK22 14.3.4 CLOCK STRETCHING Both 7-bit and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit of the SSPCON2 register allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 14.3.4.
PIC18(L)F1XK22 14.3.4.5 Clock Synchronization and the CKP bit When the CKP bit is cleared, the SCL output is forced to ‘0’. However, clearing the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS40001365F-page 150 CKP SSPOV (SSPCON1<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 6 A2 Receiving Address A5 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared by software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occur
2009-2016 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON1<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 8 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared by software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 A2 Cleared by software 3 A5 7 A1 8 A0 Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC18(L)F1XK22 14.3.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC18(L)F1XK22 MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON1 and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC18(L)F1XK22 14.3.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA, while SCL outputs the serial clock.
PIC18(L)F1XK22 14.3.7 BAUD RATE 2 In I C Master mode, the Baud Rate Generator (BRG) reload value is placed in the SSPADD register (Figure 14-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. Table 14-3 demonstrates clock rates based on instruction cycles and the BRG value loaded into SSPADD. EQUATION 14-1: Once the given operation is complete (i.e.
PIC18(L)F1XK22 14.3.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC18(L)F1XK22 14.3.8 I2C MASTER MODE START CONDITION TIMING Note: To initiate a Start condition, the user sets the Start Enable bit, SEN bit of the SSPCON2 register. If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count. If SCL and SDA are both sampled high when the Baud Rate Generator times out (TBRG), the SDA pin is driven low.
PIC18(L)F1XK22 14.3.9 I2C MASTER MODE REPEATED START CONDITION TIMING Note 1: If RSEN is programmed while any other event is in progress, it will not take effect. A Repeated Start condition occurs when the RSEN bit of the SSPCON2 register is programmed high and the I2C logic module is in the Idle state. When the RSEN bit is set, the SCL pin is asserted low. When the SCL pin is sampled low, the Baud Rate Generator is loaded and begins counting.
PIC18(L)F1XK22 14.3.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification parameter SP106).
DS40001365F-page 160 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared by software 2 6 7 8 9 After Start condition, SEN cleared by hardware SSPBUF written 1 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W start transmit A7 Transmit Address to Slave 3 D5 4 D4 5 D3 6 D2 7 D1 8 D0 SSPBUF is written by software Cleared by software service routine from SSP interrupt 2 D6 Transmitting
2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 14.3.12 ACKNOWLEDGE SEQUENCE TIMING 14.3.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN bit of the SSPCON2 register. At the end of a receive/transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to ‘0’.
PIC18(L)F1XK22 FIGURE 14-24: STOP CONDITION RECEIVE OR TRANSMIT MODE SCL = 1 for TBRG, followed by SDA = 1 for TBRG after SDA sampled high. P bit (SSPSTAT<4>) is set. Write to SSPCON2, set PEN PEN bit (SSPCON2<2>) is cleared by hardware and the SSPIF bit is set Falling edge of 9th clock TBRG SCL SDA ACK P TBRG TBRG TBRG SCL brought high after TBRG SDA asserted low before rising edge of clock to setup Stop condition Note: TBRG = one Baud Rate Generator period. 14.3.
PIC18(L)F1XK22 FIGURE 14-25: BUS COLLISION TIMING FOR TRANSMIT AND ACKNOWLEDGE Data changes while SCL = 0 SDA line pulled low by another source SDA released by master Sample SDA. While SCL is high, data doesn’t match what is driven by the master. Bus collision has occurred. SDA SCL Set bus collision interrupt (BCLIF) BCLIF DS40001365F-page 164 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 14.3.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 14-26). SCL is sampled low before SDA is asserted low (Figure 14-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 14-28).
PIC18(L)F1XK22 FIGURE 14-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC18(L)F1XK22 14.3.17.2 Bus Collision During a Repeated Start Condition If SDA is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ‘0’, Figure 14-29). If SDA is sampled high, the BRG is reloaded and begins counting. If SDA goes from high-to-low before the BRG times out, no bus collision occurs because no two masters can assert SDA at exactly the same time.
PIC18(L)F1XK22 14.3.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 14-31).
PIC18(L)F1XK22 TABLE 14-4: Name SUMMARY OF REGISTERS ASSOCIATED WITH I2C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page 248 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP IPR2 OSCFIP C1IP C2IP EEIP BCLIP — TMR3IP — 248 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248 PIE2 OSCFIE C1IE C2IE EEIE BCLIE — TMR3IE — 248 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248 OSCFIF C1IF C2IF EEIF BCLIF — TMR3IF — 248 PIR2
PIC18(L)F1XK22 15.0 The EUSART module includes the following capabilities: ENHANCED UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (EUSART) • • • • • • • • • • The Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) module is a serial I/O communications peripheral. It contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution.
PIC18(L)F1XK22 FIGURE 15-2: EUSART RECEIVE BLOCK DIAGRAM SPEN CREN RX/DT pin Baud Rate Generator Data Recovery FOSC BRG16 SPBRGH SPBRG Multiplier x4 x16 x64 SYNC 1 X 0 0 0 BRGH X 1 1 0 0 BRG16 X 1 0 1 0 Stop RCIDL RSR Register MSb Pin Buffer and Control +1 OERR (8) ••• 7 1 LSb 0 START RX9 ÷n n FERR RX9D RCREG Register 8 FIFO Data Bus RCIF RCIE Interrupt The operation of the EUSART module is controlled through three registers: • Transmit Status and Control (TXSTA) • R
PIC18(L)F1XK22 15.1 EUSART Asynchronous Mode The EUSART transmits and receives data using the standard non-return-to-zero (NRZ) format. NRZ is implemented with two levels: a VOH Mark state which represents a ‘1’ data bit, and a VOL Space state which represents a ‘0’ data bit. NRZ refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission.
PIC18(L)F1XK22 15.1.1.5 TSR Status 15.1.1.7 The TRMT bit of the TXSTA register indicates the status of the TSR register. This is a read-only bit. The TRMT bit is set when the TSR register is empty and is cleared when a character is transferred to the TSR register from the TXREG. The TRMT bit remains clear until all bits have been shifted out of the TSR register. No interrupt logic is tied to this bit, so the user needs to poll this bit to determine the TSR status. 1. 2. 3.
PIC18(L)F1XK22 FIGURE 15-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK) Write to TXREG Word 1 BRG Output (Shift Clock) RB7/TX/CK pin Start bit bit 1 Word 1 bit 7/8 Stop bit Start bit bit 0 Word 2 1 TCY TRMT bit (Transmit Shift Reg. Empty Flag) Word 1 Transmit Shift Reg Word 2 Transmit Shift Reg This timing diagram shows two consecutive transmissions. TABLE 15-1: Name bit 0 1 TCY TXIF bit (Interrupt Reg.
PIC18(L)F1XK22 15.1.2 EUSART ASYNCHRONOUS RECEIVER The Asynchronous mode would typically be used in RS-232 systems. The receiver block diagram is shown in Figure 15-2. The data is received on the RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial Receive Shift Register (RSR) operates at the bit rate.
PIC18(L)F1XK22 15.1.2.4 Receive Interrupts The RCIF interrupt flag bit of the PIR1 register is set whenever the EUSART receiver is enabled and there is an unread character in the receive FIFO. The RCIF interrupt flag bit is read-only, it cannot be set or cleared by software.
PIC18(L)F1XK22 15.1.2.9 Asynchronous Reception Set-up 15.1.2.10 1. Initialize the SPBRGH:SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 15.3 “EUSART Baud Rate Generator (BRG)”). 2. Enable the serial port by setting the SPEN bit and the RX/DT pin TRIS bit. The SYNC bit must be clear for asynchronous operation. 3. If interrupts are desired, set the RCIE interrupt enable bit and set the GIE and PEIE bits of the INTCON register. 4.
PIC18(L)F1XK22 TABLE 15-2: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN 247 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 248 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248 PIR1 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248 CREN ADDEN FERR
PIC18(L)F1XK22 15.2 Clock Accuracy with Asynchronous Operation The factory calibrates the internal oscillator block output (HFINTOSC). However, the HFINTOSC frequency may drift as VDD or temperature changes, and this directly affects the asynchronous baud rate. Two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. REGISTER 15-1: The first (preferred) method uses the OSCTUNE register to adjust the HFINTOSC output.
PIC18(L)F1XK22 REGISTER 15-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RX/DT and TX/CK pins as serial port pins) 0 = Serial port disabled (held in Reset) bit 6 RX9
PIC18(L)F1XK22 REGISTER 15-3: BAUDCON: BAUD RATE CONTROL REGISTER R-0 R-1 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 ABDOVF RCIDL DTRXP CKTXP BRG16 — WUE ABDEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 ABDOVF: Auto-Baud Detect Overflow bit Asynchronous mode: 1 = Auto-baud timer overflowed 0 = Auto-baud timer did not overflow Synchronous mode: Don’t care bit 6 R
PIC18(L)F1XK22 15.3 EUSART Baud Rate Generator (BRG) The Baud Rate Generator (BRG) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous EUSART operation. By default, the BRG operates in 8-bit mode. Setting the BRG16 bit of the BAUDCON register selects 16-bit mode. If the system clock is changed during an active receive operation, a receive error or data loss may result.
PIC18(L)F1XK22 TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES SYNC = 0, BRGH = 0, BRG16 = 0 BAUD RATE FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRG value (decimal) 300 — — — — — — — — — — — — 1200 — — — 1200 0.00 239 1202 0.16 155 1200 0.00 143 Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 2400 — — — 2400 0.00 119 2404 0.
PIC18(L)F1XK22 TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 0 BAUD RATE FOSC = 8.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 4.000 MHz Actual Rate % Error SPBRG value (decimal) FOSC = 3.6864 MHz Actual Rate FOSC = 1.000 MHz % Error SPBRG value (decimal) Actual Rate % Error SPBRG value (decimal) 300 1200 — — — — — — — 1202 — 0.16 — 207 — 1200 — 0.00 — 191 300 1202 0.16 0.16 207 51 2400 2404 0.16 207 2404 0.
PIC18(L)F1XK22 TABLE 15-5: BAUD RATES FOR ASYNCHRONOUS MODES (CONTINUED) SYNC = 0, BRGH = 1, BRG16 = 1 or SYNC = 1, BRG16 = 1 BAUD RATE FOSC = 48.000 MHz FOSC = 18.432 MHz FOSC = 12.000 MHz FOSC = 11.0592 MHz Actual Rate % Error SPBRGH :SPBRG (decimal) 300 1200 300 1200 0.00 0.00 39999 9999 300.0 1200 0.00 0.00 15359 3839 300 1200 0.00 0.00 9999 2499 300.0 1200 0.00 0.00 9215 2303 2400 2400 0.00 4999 2400 0.00 1919 2400 0.00 1249 2400 0.
PIC18(L)F1XK22 15.3.1 AUTO-BAUD DETECT The EUSART module supports automatic detection and calibration of the baud rate. In the Auto-Baud Detect (ABD) mode, the clock to the BRG is reversed. Rather than the BRG clocking the incoming RX signal, the RX signal is timing the BRG. The Baud Rate Generator is used to time the period of a received 55h (ASCII “U”), which is the Sync character for the LIN bus. The unique feature of this character is that it has five rising edges including the Stop bit edge.
PIC18(L)F1XK22 15.3.2 AUTO-BAUD OVERFLOW During the course of automatic baud detection, the ABDOVF bit of the BAUDCON register will be set if the baud rate counter overflows before the fifth rising edge is detected on the RX pin. The ABDOVF bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the SPBRGH:SPBRG register pair. After the ABDOVF has been set, the counter continues to count until the fifth rising edge is detected on the RX pin.
PIC18(L)F1XK22 FIGURE 15-7: AUTO-WAKE-UP BIT (WUE) TIMING DURING NORMAL OPERATION Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Auto Cleared Bit set by user WUE bit RX/DT Line RCIF Note 1: Cleared due to User Read of RCREG The EUSART remains in Idle while the WUE bit is set.
PIC18(L)F1XK22 15.3.4 BREAK CHARACTER SEQUENCE The EUSART module has the capability of sending the special Break character sequences that are required by the LIN bus standard. A Break character consists of a Start bit, followed by 12 ‘0’ bits and a Stop bit. To send a Break character, set the SENDB and TXEN bits of the TXSTA register. The Break character transmission is then initiated by a write to the TXREG. The value of data written to TXREG will be ignored and all ‘0’s will be transmitted.
PIC18(L)F1XK22 15.4 EUSART Synchronous Mode Synchronous serial communications are typically used in systems with a single master and one or more slaves. The master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. Slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. There are two signal lines in Synchronous mode: a bidirectional data line and a clock line.
PIC18(L)F1XK22 15.4.1.5 1. 2. Synchronous Master Transmission Set-up 3. Initialize the SPBRGH, SPBRG register pair and the BRGH and BRG16 bits to achieve the desired baud rate (see Section 15.3 “EUSART Baud Rate Generator (BRG)”). Enable the synchronous master serial port by setting bits SYNC, SPEN and CSRC. Set the TRIS bits corresponding to the RX/DT and TX/CK I/O pins. 4. 5. 6. FIGURE 15-10: 7. 8. Disable Receive mode by clearing bits SREN and CREN. Enable Transmit mode by setting the TXEN bit.
PIC18(L)F1XK22 TABLE 15-7: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 BAUDCON ABDOVF RCIDL DTRXP CKTXP BRG16 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE Bit 1 Bit 0 Reset Values on page — WUE ABDEN 247 TMR0IF INT0IF RABIF 245 Bit 2 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 248 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248 SPEN RX9 SREN
PIC18(L)F1XK22 15.4.1.9 Receiving 9-bit Characters 3. 4. Ensure bits CREN and SREN are clear. If using interrupts, set the GIE and PEIE bits of the INTCON register and set RCIE. 5. If 9-bit reception is desired, set bit RX9. 6. Start reception by setting the SREN bit or for continuous reception, set the CREN bit. 7. Interrupt flag bit RCIF will be set when reception of a character is complete. An interrupt will be generated if the enable bit RCIE was set. 8.
PIC18(L)F1XK22 TABLE 15-8: Name REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION Bit 7 BAUDCON ABDOVF INTCON Bit 6 RCIDL GIE/GIEH PEIE/GIEL Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page DTRXP CKTXP BRG16 — WUE ABDEN 247 TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245 IPR1 — ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 248 PIE1 — ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 248 — ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 248 PIR1 RCREG RCSTA EUSA
PIC18(L)F1XK22 15.4.2 SYNCHRONOUS SLAVE MODE The following bits are used to configure the EUSART for synchronous slave operation: • • • • • SYNC = 1 CSRC = 0 SREN = 0 (for transmit); SREN = 1 (for receive) CREN = 0 (for transmit); CREN = 1 (for receive) SPEN = 1 1. 2. 3. 4. Setting the SYNC bit of the TXSTA register configures the device for synchronous operation. Clearing the CSRC bit of the TXSTA register configures the device as a slave.
PIC18(L)F1XK22 15.4.2.3 EUSART Synchronous Slave Reception 15.4.2.4 The operation of the Synchronous Master and Slave modes is identical (Section 15.4.1.6 “Synchronous Master Reception”), with the following exceptions: 1. • Sleep • CREN bit is always set, therefore the receiver is never Idle • SREN bit, which is a “don't care” in Slave mode 2. A character may be received while in Sleep mode by setting the CREN bit prior to entering Sleep.
PIC18(L)F1XK22 16.0 ANALOG-TO-DIGITAL CONVERTER (ADC) MODULE The Analog-to-Digital Converter (ADC) allows conversion of an analog input signal to a 10-bit binary representation of that signal. This device uses analog inputs, which are multiplexed into a single sample and hold circuit. The output of the sample and hold is connected to the input of the converter.
PIC18(L)F1XK22 16.1 ADC Configuration When configuring and using the ADC the following functions must be considered: • • • • • • Port configuration Channel selection ADC voltage reference selection ADC conversion clock source Interrupt control Results formatting 16.1.1 PORT CONFIGURATION The ANSEL, ANSELH, TRISA, TRISB and TRISE registers all configure the A/D port pins.
PIC18(L)F1XK22 16.1.6 INTERRUPTS This interrupt can be generated while the device is operating or while in Sleep. If the device is in Sleep, the interrupt will wake-up the device. Upon waking from Sleep, the next instruction following the SLEEP instruction is always executed. If the user is attempting to wake-up from Sleep and resume in-line code execution, the global interrupt must be disabled. If the global interrupt is enabled, execution will switch to the Interrupt Service Routine.
PIC18(L)F1XK22 16.2 Figure 16-3 shows the operation of the A/D converter after the GO bit has been set and the ACQT<2:0> bits are cleared. A conversion is started after the following instruction to allow entry into SLEEP mode before the conversion begins. ADC Operation 16.2.1 STARTING A CONVERSION To enable the ADC module, the ADON bit of the ADCON0 register must be set to a ‘1’.
PIC18(L)F1XK22 16.2.2 COMPLETION OF A CONVERSION When the conversion is complete, the ADC module will: • Clear the GO/DONE bit • Set the ADIF flag bit • Update the ADRESH:ADRESL registers with new conversion result 16.2.3 DISCHARGE The discharge phase is used to initialize the value of the capacitor array. The array is discharged after every sample.
PIC18(L)F1XK22 16.2.9 A/D CONVERSION PROCEDURE This is an example procedure for using the ADC to perform an Analog-to-Digital conversion: 1. 2. 3. 4. 5. 6. 7. 8.
PIC18(L)F1XK22 16.2.10 ADC REGISTER DEFINITIONS The following registers are used to control the operation of the ADC. Note: Analog pin control is performed by the ANSEL and ANSELH registers. For ANSEL and ANSELH registers, see Register 8-14 and Register 8-15, respectively.
PIC18(L)F1XK22 REGISTER 16-2: ADCON1: A/D CONTROL REGISTER 1 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-4 Unimplemented: Read as ‘0’ bit 3-2 PVCFG<1:0>: Positive Voltage Reference select bit 00 = Positive voltage reference supplied internally by VDD.
PIC18(L)F1XK22 REGISTER 16-3: ADCON2: A/D CONTROL REGISTER 2 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 x = Bit is unknown ADFM: A/D Conversion Result Format Select bit 1 = Right justified 0 = Left justified bit 6 Unimplemented: Read as ‘0’ bit 5-3 ACQT<2:0>: A/D Acquisition Time Se
PIC18(L)F1XK22 REGISTER 16-4: ADRESH: ADC RESULT REGISTER HIGH (ADRESH) ADFM = 0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x ADRES9 ADRES8 ADRES7 ADRES6 ADRES5 ADRES4 ADRES3 ADRES2 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-0 x = Bit is unknown ADRES<9:2>: ADC Result Register bits Upper 8 bits of 10-bit conversion result REGISTER 16-5: ADRESL: ADC RESULT REGISTER LOW
PIC18(L)F1XK22 16.3 A/D Acquisition Requirements For the ADC to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The Analog Input model is shown in Figure 16-5. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 16-5.
PIC18(L)F1XK22 FIGURE 16-5: ANALOG INPUT MODEL VDD ANx Rs CPIN 5 pF VA VT = 0.6V VT = 0.6V RIC 1k Sampling Switch SS Rss CHOLD = 13.5 pF I LEAKAGE(1) Legend: CPIN = Input Capacitance = Threshold Voltage VT I LEAKAGE = Leakage current at the pin due to various junctions RIC = Interconnect Resistance SS = Sampling Switch CHOLD = Sample/Hold Capacitance Note 1: VDD Discharge Switch VSS/VREF- 3.5V 3.0V 2.5V 2.0V 1.5V .1 1 10 Rss (k) 100 See Section 26.0 “Electrical Specifications”.
PIC18(L)F1XK22 TABLE 16-2: Name REGISTERS ASSOCIATED WITH A/D OPERATION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page ADRESH A/D Result Register, High Byte 247 ADRESL A/D Result Register, Low Byte 247 ADCON0 — — CHS3 CHS2 CHS1 CHS0 GO/DONE ADON 247 ADCON1 — — — — PVCFG1 PVCFG0 NVCFG1 NVCFG0 247 ADCON2 ADFM — ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 247 ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 248 — — — — ANS11 ANS10 ANS9 A
PIC18(L)F1XK22 17.0 COMPARATOR MODULE Comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. The comparators are very useful mixed signal building blocks because they provide analog functionality independent of the program execution.
PIC18(L)F1XK22 FIGURE 17-2: COMPARATOR C1 SIMPLIFIED BLOCK DIAGRAM C1CH<1:0> 2 D Q1 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 To Data Bus Q EN RD_CM1CON0 D Q3*RD_CM1CON0 Q Set C1IF EN CL NReset C1ON(1) C1R C1VINC1IN+ DAC Output FVR 0 MUX 1 C1VIN+ 0 MUX C1VREF 1 - C1SP To PWM Logic C1OUT C1 + C1POL C1SYNC C1OE 0 C1RSEL D From TMR1L[0] Q 1 C1OUT (4) SYNCC1OUT Note 1: 2: 3: 4: 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 17-3: COMPARATOR C2 SIMPLIFIED BLOCK DIAGRAM D Q1 To Data Bus Q EN RD_CM2CON0 C2CH<1:0> 2 D Set C2IF Q Q3*RD_CM2CON0 C12IN0- 0 C12IN1C12IN2- 1 MUX 2 C12IN3- 3 C2R EN CL NRESET C2ON(1) C2VINC2VIN+ To PWM Logic C2OUT C2 C2SP C2SYNC C2POL 0 C2IN+ DAC Output FVR 0 MUX 1 0 MUX C2VREF 1 D From TMR1L[0] (4) Q C20E C2OUT pin 1 SYNCC2OUT C2RSEL Note 1: 2: 3: 4: DS40001365F-page 212 When C2ON = 0, the C2 comparator will produce a ‘0’ output to the XOR Gate.
PIC18(L)F1XK22 17.2 Comparator Control Each comparator has a separate control and Configuration register: CM1CON0 for Comparator C1 and CM2CON0 for Comparator C2. In addition, Comparator C2 has a second control register, CM2CON1, for controlling the interaction with Timer1 and simultaneous reading of both comparator outputs.
PIC18(L)F1XK22 17.4 Comparator Interrupt Operation The comparator interrupt flag can be set whenever there is a change in the output value of the comparator. Changes are recognized by means of a mismatch circuit which consists of two latches and an exclusiveor gate (see Figure 17-2 and Figure 17-3). One latch is updated with the comparator output level when the CMxCON0 register is read. This latch retains the value until the next read of the CMxCON0 register or the occurrence of a Reset.
PIC18(L)F1XK22 17.5 Operation During Sleep The comparator, if enabled before entering Sleep mode, remains active during Sleep. The additional current consumed by the comparator is shown separately in Section 26.0 “Electrical Specifications”. If the comparator is not used to wake the device, power consumption can be minimized while in Sleep mode by turning off the comparator. Each comparator is turned off by clearing the CxON bit of the CMxCON0 register.
PIC18(L)F1XK22 REGISTER 17-1: CM1CON0: COMPARATOR 1 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C1ON: Comparator C1 Enable bit 1 = Comparator C1 is enabled 0 = Comparator C1 is disabled bit 6 C1OUT: Comparator C1 Output bit If C1POL = 1 (inverted polarity): C1OUT = 0
PIC18(L)F1XK22 REGISTER 17-2: CM2CON0: COMPARATOR 2 CONTROL REGISTER 0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 C2ON: Comparator C2 Enable bit 1 = Comparator C2 is enabled 0 = Comparator C2 is disabled bit 6 C2OUT: Comparator C2 Output bit If C2POL = 1 (inverted polarity): C2OUT = 0
PIC18(L)F1XK22 17.7 Analog Input Connection Considerations A simplified circuit for an analog input is shown in Figure 17-6. Since the analog input pins share their connection with a digital input, they have reverse biased ESD protection diodes to VDD and VSS. The analog input, therefore, must be between VSS and VDD. If the input voltage deviates from this range by more than 0.6V in either direction, one of the diodes is forward biased and a latch-up may occur.
PIC18(L)F1XK22 17.8 Additional Comparator Features There are four additional comparator features: • • • • Simultaneous read of comparator outputs Internal reference selection Hysteresis selection Output Synchronization 17.8.1 SIMULTANEOUS COMPARATOR OUTPUT READ The MC1OUT and MC2OUT bits of the CM2CON1 register are mirror copies of both comparator outputs. The ability to read both outputs simultaneously from a single register eliminates the timing skew of reading separate registers.
PIC18(L)F1XK22 REGISTER 17-3: CMCON0: COMPARATOR 2 CONTROL REGISTER 1 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7 MC1OUT: Mirror Copy of C1OUT bit bit 6 MC2OUT: Mirror Copy of C2OUT bit bit 5 C1RSEL: Comparator C1 Reference Select bit 1 = FVR routed to C1VREF input 0 = CVREF/
PIC18(L)F1XK22 TABLE 17-2: Name REGISTERS ASSOCIATED WITH COMPARATOR MODULE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on page ANSEL ANS7 ANS6 ANS5 ANS4 ANS3 ANS2 ANS1 ANS0 248 CM1CON0 C1ON C1OUT C1OE C1POL C1SP C1R C1CH1 C1CH0 248 CM2CON0 C2ON C2OUT C2OE C2POL C2SP C2R C2CH1 C2CH0 248 CM2CON1 MC1OUT MC2OUT C1RSEL C2RSEL C1HYS C2HYS C1SYNC C2SYNC 248 INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RABIE TMR0IF INT0IF RABIF 245 IPR2 OSCFI
PIC18(L)F1XK22 18.0 18.1.1 POWER-MANAGED MODES The SCS<1:0> bits allow the selection of one of three clock sources for power-managed modes. They are: PIC18(L)F1XK22 devices offer a total of seven operating modes for more efficient power management. These modes provide a variety of options for selective power conservation in applications where resources may be limited (i.e., battery-powered devices).
PIC18(L)F1XK22 18.1.3 MULTIPLE FUNCTIONS OF THE SLEEP COMMAND The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN bit of the OSCCON register at the time the instruction is executed. All clocks stop and minimum power is consumed when SLEEP is executed with the IDLEN bit cleared. The system clock continues to supply a clock to the peripherals but is disconnected from the CPU when SLEEP is executed with the IDLEN bit set. 18.2 18.2.
PIC18(L)F1XK22 18.3 Sleep Mode 18.4 The Power-Managed Sleep mode in the PIC18(L)F1XK22 devices is identical to the legacy Sleep mode offered in all other PIC microcontroller devices. It is entered by clearing the IDLEN bit of the OSCCON register and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 18-1) and all clock source status bits are cleared. Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate.
PIC18(L)F1XK22 18.4.1 PRI_IDLE MODE 18.4.2 This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm-up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction.
PIC18(L)F1XK22 18.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block from the HFINTOSC multiplexer output. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then set the SCS1 bit and execute SLEEP.
PIC18(L)F1XK22 18.5.3 EXIT BY RESET 18.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Exiting Sleep and Idle modes by Reset causes code execution to restart at address 0. See Section 22.0 “Reset” for more details. Certain exits from power-managed modes do not invoke the OST at all. There are two cases: The exit delay time from Reset to the start of code execution depends on both the clock sources before and after the wake-up and the type of oscillator. Exit delays are summarized in Table 18-2.
PIC18(L)F1XK22 19.0 SR LATCH 19.2 The SRQEN and SRNQEN bits of the SRCON0 register control the latch output selection. Both of the SR latch’s outputs may be directly output to an independent I/O pin. Control is determined by the state of bits SRQEN and SRNQEN in registers SRCON0. The module consists of a single SR latch with multiple Set and Reset inputs as well as selectable latch output.
PIC18(L)F1XK22 TABLE 19-1: SRCLK SRCLK FREQUENCY TABLE Divider FOSC = 20 MHz FOSC = 16 MHz FOSC = 8 MHz FOSC = 4 MHz FOSC = 1 MHz 111 512 25.6 s 32 s 64 s 128 s 512 s 110 256 12.8 s 16 s 32 s 64 s 256 s 101 128 6.4 s 8 s 16 s 32 s 128 s 100 64 3.2 s 4 s 8 s 16 s 64 s 011 32 1.6 s 2 s 4 s 8 s 32 s 010 16 0.8 s 1 s 2 s 4 s 16 s 001 8 0.4 s 0.5 s 1 s 2 s 8 s 000 4 0.2 s 0.25 s 0.
PIC18(L)F1XK22 REGISTER 19-2: SRCON1: SR LATCH CONTROL REGISTER 1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SRSPE SRSCKE SRSC2E SRSC1E SRRPE SRRCKE SRRC2E SRRC1E bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented C = Clearable only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 SRSPE: SR Latch Peripheral Set Enable bit 1 = INT1 pin status sets SR latch 0 = INT1 pin status has no effect on SR latch bit 6 SRSCKE: S
PIC18(L)F1XK22 20.0 FIXED VOLTAGE REFERENCE (FVR) 20.1 The Fixed Voltage Reference, or FVR, is a stable voltage reference, independent of VDD, with 1.024V, 2.048V or 4.096V selectable output levels. The output of the FVR can be configured to supply a reference voltage to the following: • • • • ADC input channel ADC positive reference Comparator positive input Digital-to-Analog Converter (DAC) The FVR can be enabled by setting the FVR1EN bit of the VREFCON0 register.
PIC18(L)F1XK22 20.
PIC18(L)F1XK22 21.0 DIGITAL-TO-ANALOG CONVERTER (DAC) MODULE The Digital-to-Analog Converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. The negative voltage source is disabled by setting the D1LPS bit in the VREFCON1 register. Clearing the D1LPS bit in the VREFCON1 register disables the positive voltage source. 21.
PIC18(L)F1XK22 FIGURE 21-1: DIGITAL-TO-ANALOG CONVERTER BLOCK DIAGRAM Digital-to-Analog Converter (DAC) Reserved 11 10 FVR1BUF1 VREF+ VSRC+ 01 00 VDD DAC1R<4:0> 5 R 2 R D1PSS<1:0> R D1EN D1LPS 11111 11110 R 32 Steps R 32-to-1 MUX R DAC Output (to Comparators and ADC Modules) R R 00001 CVREF/DAC1OUT 00000 DAC1OE D1NSS FIGURE 21-2: VREF- 1 VSS 0 VSRC- VOLTAGE REFERENCE OUTPUT BUFFER EXAMPLE PIC® MCU DAC Module R Voltage Reference Output Impedance DS40001365F-page 234 DAC1OUT
PIC18(L)F1XK22 21.7 Operation During Sleep 21.8 When the device wakes up from Sleep through an interrupt or a Watchdog Timer time-out, the contents of the VREFCON1 register are not affected. To minimize current consumption in Sleep mode, the voltage reference should be disabled. 21.
PIC18(L)F1XK22 REGISTER 21-2: VREFCON2: VOLTAGE REFERENCE CONTROL REGISTER 1 U-0 U-0 U-0 — — — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DAC1R<4:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets ‘1’ = Bit is set ‘0’ = Bit is cleared bit 7-5 Unimplemented: Read as ‘0’ bit 4-0 DAC1R<4:0>: DAC Voltage Output Select bits VOUT = ((VSRC+) - (VSRC-))*(DAC1R<4:0>/(25
PIC18(L)F1XK22 22.0 RESET The PIC18(L)F1XK22 devices differentiate between various kinds of Reset: a) b) c) d) e) f) g) h) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Programmable Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset This section discusses Resets generated by MCLR, POR and BOR and covers the operation of the various start-up timers.
PIC18(L)F1XK22 REGISTER 22-1: RCON: RESET CONTROL REGISTER R/W-0 R/W-1 U-0 R/W-1 R-1 R-1 R/W-0 R/W-0 IPEN SBOREN(1) — RI TO PD POR(2) BOR bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6 SBOREN: BOR Softwa
PIC18(L)F1XK22 22.2 Master Clear (MCLR) The MCLR pin provides a method for triggering an external Reset of the device. A Reset is generated by holding the pin low. These devices have a noise filter in the MCLR Reset path which detects and ignores small pulses. FIGURE 22-2: In PIC18(L)F1XK22 devices, the MCLR input can be disabled with the MCLRE Configuration bit. When MCLR is disabled, the pin becomes a digital input. See Section 8.1 “PORTA, TRISA and LATA Registers” for more information. 22.
PIC18(L)F1XK22 22.4 Brown-out Reset (BOR) PIC18(L)F1XK22 devices implement a BOR circuit that provides the user with a number of configuration and power-saving options. The BOR is controlled by the BORV<1:0> and BOREN<1:0> bits of the CONFIG2L Configuration register. There are a total of four BOR configurations which are summarized in Table 22-1. The BOR threshold is set by the BORV<1:0> bits.
PIC18(L)F1XK22 22.5 Device Reset Timers PIC18(L)F1XK22 devices incorporate three separate on-chip timers that help regulate the Power-on Reset process. Their main function is to ensure that the device clock is stable before code is executed. These timers are: • Power-up Timer (PWRT) • Oscillator Start-up Timer (OST) • PLL Lock Time-out 22.5.1 POWER-UP TIMER (PWRT) The Power-up Timer (PWRT) of PIC18(L)F1XK22 devices is an 11-bit counter which uses the LFINTOSC source as the clock input.
PIC18(L)F1XK22 FIGURE 22-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 FIGURE 22-4: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 22-5: VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS40001365F-page 242 20
PIC18(L)F1XK22 FIGURE 22-6: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 5V VDD 0V MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 22-7: TIME-OUT SEQUENCE ON POR W/PLL ENABLED (MCLR TIED TO VDD) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT OST TIME-OUT TOST TPLL PLL TIME-OUT INTERNAL RESET Note: TOST = 1024 clock cycles. TPLL 2 ms max. First three stages of the PWRT timer. 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 22.6 Reset State of Registers Some registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. All other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register, RI, TO, PD, POR and BOR, are set or cleared differently in different Reset situations, as indicated in Table 22-3.
PIC18(L)F1XK22 TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets TOSU FFFh ---0 0000 ---0 0000 ---0 uuuu(3) TOSH FFEh 0000 0000 0000 0000 uuuu uuuu(3) TOSL FFDh 0000 0000 0000 0000 uuuu uuuu(3) STKPTR FFCh 00-0 0000 uu-0 0000 uu-u uuuu(3) PCLATU FFBh ---0 0000 ---0 0000 ---u uuuu PCLATH FFAh 0000 0000 0000 0000 uuuu uuuu PCL FF9h 0000 0000 0000 0000 TBLPTRU FF8h ---0
PIC18(L)F1XK22 TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt FSR1H FE2h ---- 0000 ---- 0000 ---- uuuu FSR1L FE1h xxxx xxxx uuuu uuuu uuuu uuuu BSR FE0h ---- 0000 ---- 0000 ---- uuuu INDF2 FDFh N/A N/A N/A POSTINC2 FDEh N/A N/A N/A POSTDEC2 FDDh N/A N/A N/A PREINC2 FDCh N/A N/A N/A PLUSW2 FDBh N/A N/A N/A FSR2H FDAh -
PIC18(L)F1XK22 TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt ADRESH FC4h xxxx xxxx uuuu uuuu uuuu uuuu ADRESL FC3h xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 FC2h --00 0000 --00 0000 --uu uuuu ADCON1 FC1h ---- 0000 ---- 0000 ---- uuuu ADCON2 FC0h 0-00 0000 0-00 0000 u-uu uuuu CCPR1H FBFh xxxx xxxx uuuu uuuu uuuu uuuu CCPR1L FBEh xxx
PIC18(L)F1XK22 TABLE 22-4: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Address Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset, RESET Instruction, Stack Resets Wake-up via WDT or Interrupt IPR2 FA2h 1111 1-1- 1111 1-1- uuuu u-u- PIR2 FA1h 0000 0-0- 0000 0-0- uuuu u-u-(1) PIE2 FA0h 0000 0-0- 0000 0-0- uuuu u-u- IPR1 F9Fh -111 1111 -111 1111 -uuu uuuu PIR1 F9Eh -000 0000 -000 0000 -uuu uuuu(1) PIE1 F9Dh -000 0000 -000 0000 -uuu uuuu OSCTUNE F9Bh 0000 000
PIC18(L)F1XK22 23.0 SPECIAL FEATURES OF THE CPU PIC18(L)F1XK22 devices include several features intended to maximize reliability and minimize cost through elimination of external components.
PIC18(L)F1XK22 23.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’) or left unprogrammed (read as ‘1’) to select various device configurations. These bits are mapped starting at program memory location 300000h. The user will note that address 300000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (300000h-3FFFFFh), which can only be accessed using table reads and table writes.
PIC18(L)F1XK22 REGISTER 23-1: CONFIG1H: CONFIGURATION REGISTER 1 HIGH R/P-0 R/P-0 R/P-1 R/P-0 R/P-0 R/P-1 R/P-1 R/P-1 IESO FCMEN PCLKEN PLL_EN FOSC3 FOSC2 FOSC1 FOSC0 bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 IESO: Internal/External Oscillator Switchover bit 1 = Oscillator Switchover mode enabled 0 = Oscillator Switchover mode disabled bit 6 FCMEN: Fail-Safe Clock Mon
PIC18(L)F1XK22 REGISTER 23-2: U-0 CONFIG2L: CONFIGURATION REGISTER 2 LOW U-0 — — U-0 — R/P-1 BORV1 R/P-1 (1) BORV0 (1) R/P-1 BOREN1 R/P-1 (2) BOREN0 bit 7 R/P-1 (2) PWRTEN(2) bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-3 BORV<1:0>: Brown-out Reset Voltage bits(1) 11 = VBOR set to 1.9V nominal 10 = VBOR set to 2.2V nominal 01 = VBOR set to 2.
PIC18(L)F1XK22 REGISTER 23-3: CONFIG2H: CONFIGURATION REGISTER 2 HIGH U-0 U-0 U-0 R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 — — — WDTPS3 WDTPS2 WDTPS1 WDTPS0 WDTEN bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7-5 Unimplemented: Read as ‘0’ bit 4-1 WDTPS<3:0>: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,02
PIC18(L)F1XK22 REGISTER 23-4: CONFIG3H: CONFIGURATION REGISTER 3 HIGH R/P-1 U-0 U-0 U-0 R/P-1 U-0 U-0 U-0 MCLRE — — — HFOFST — — — bit 7 bit 0 Legend: R = Readable bit P = Programmable bit -n = Value when device is unprogrammed U = Unimplemented bit, read as ‘0’ x = Bit is unknown bit 7 MCLRE: MCLR Pin Enable bit 1 = MCLR pin enabled; RA3 input pin disabled 0 = RA3 input pin enabled; MCLR disabled bit 6-4 Unimplemented: Read as ‘0’ bit 3 HFOFST: HFINTOSC Fast Start-up bit 1 = HF
PIC18(L)F1XK22 REGISTER 23-6: CONFIG5L: CONFIGURATION REGISTER 5 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — CP1 CP0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 CP1: Code Protection bit 1 = Block 1 not code-protected 0 = Block 1 code-protected bit 0 CP0: Code Protection bit 1 = Block 0 not code-protected 0 = Block 0 code-protected REGISTER 2
PIC18(L)F1XK22 REGISTER 23-8: CONFIG6L: CONFIGURATION REGISTER 6 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — WRT1 WRT0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 WRT1: Write Protection bit 1 = Block 1 not write-protected 0 = Block 1 write-protected bit 0 WRT0: Write Protection bit 1 = Block 0 not write-protected 0 = Block 0 write-protected
PIC18(L)F1XK22 REGISTER 23-10: CONFIG7L: CONFIGURATION REGISTER 7 LOW U-0 U-0 U-0 U-0 U-0 U-0 R/C-1 R/C-1 — — — — — — EBTR1 EBTR0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-2 Unimplemented: Read as ‘0’ bit 1 EBTR1: Table Read Protection bit 1 = Block 1 not protected from table reads executed in other blocks 0 = Block 1 protected from table reads executed in other blocks bit 0 EBTR0: Ta
PIC18(L)F1XK22 REGISTER 23-12: DEVID1: DEVICE ID REGISTER 1 FOR PIC18(L)F1XK22 R R R R R R R R DEV2 DEV1 DEV0 REV4 REV3 REV2 REV1 REV0 bit 7 bit 0 Legend: R = Readable bit U = Unimplemented bit, read as ‘0’ -n = Value when device is unprogrammed C = Clearable only bit bit 7-5 DEV<2:0>: Device ID bits 010 = PIC18(L)F13K22 011 = PIC18(L)F14K22 bit 4-0 REV<4:0>: Revision ID bits These bits are used to indicate the device revision.
PIC18(L)F1XK22 23.2 Watchdog Timer (WDT) For PIC18(L)F1XK22 devices, the WDT is driven by the LFINTOSC source. When the WDT is enabled, the clock source is also enabled. The nominal WDT period is 4 ms and has the same stability as the LFINTOSC oscillator. The 4-millisecond period of the WDT is multiplied by a 16-bit postscaler. Any output of the WDT postscaler is selected by a multiplexer, controlled by bits in Configuration register 2H. Available periods range from 4 ms to 131.072 seconds (2.18 minutes).
PIC18(L)F1XK22 23.2.1 CONTROL REGISTER Register 23-14 shows the WDTCON register. This is a readable and writable register which contains a control bit that allows software to override the WDT enable Configuration bit, but only if the Configuration bit has disabled the WDT.
PIC18(L)F1XK22 FIGURE 23-2: CODE-PROTECTED PROGRAM MEMORY FOR PIC18(L)F1XK22 Device Address (from/to) 14K22 BBSIZ = 1 0000h 03FFh 13K22 BBSIZ = 0 BBSIZ = 1 Boot Block, 4 KB Boot Block, 2 KB Boot Block, 2 KB CPB, WRTB, EBTRB CPB, WRTB, EBTRB CPB, WRTB, EBTRB 0400h 07FFh Block 0 6 KB CP0, WRT0, EBTR0 0800h 0BFFh 0C00h Block 0 2 KB CP0, WRT0, EBTR0 BBSIZ = 0 Boot Block, 1 KB CPB, WRTB, EBTRB Block 0 1.
PIC18(L)F1XK22 TABLE 23-3: SUMMARY OF CODE PROTECTION REGISTERS File Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 300008h CONFIG5L — — — — — — CP1 CP0 300009h CONFIG5H CPD CPB — — — — — — 30000Ah CONFIG6L — — — — — — WRT1 WRT0 — — — — — EBTR0 — 30000Bh CONFIG6H WRTD WRTB WRTC(1) 30000Ch CONFIG7L — — — — — — EBTR1 30000Dh CONFIG7H — EBTRB — — — — — Legend: Shaded cells are unimplemented.
PIC18(L)F1XK22 FIGURE 23-4: EXTERNAL BLOCK TABLE READ (EBTRn) DISALLOWED Register Values Program Memory Configuration Bit Settings 000000h 0007FFh 000800h TBLPTR = 0008FFh WRTB, EBTRB = 11 WRT0, EBTR0 = 10 001FFFh 002000h PC = 003FFEh WRT1, EBTR1 = 11 TBLRD* 003FFFh 004000h WRT2, EBTR2 = 11 005FFFh 006000h WRT3, EBTR3 = 11 007FFFh Results: All table reads from external blocks to Blockn are disabled whenever EBTRn = 0. TABLAT register returns a value of ‘0’.
PIC18(L)F1XK22 23.3.2 DATA EEPROM CODE PROTECTION The entire data EEPROM is protected from external reads and writes by two bits: CPD and WRTD. CPD inhibits external reads and writes of data EEPROM. WRTD inhibits internal and external writes to data EEPROM. The CPU can always read data EEPROM under normal operation, regardless of the protection bit settings. 23.3.3 CONFIGURATION REGISTER PROTECTION The Configuration registers can be write-protected.
PIC18(L)F1XK22 24.0 INSTRUCTION SET SUMMARY PIC18(L)F1XK22 devices incorporate the standard set of 75 PIC18 core instructions, as well as an extended set of eight new instructions, for the optimization of code that is recursive or that utilizes a software stack. The extended set is discussed later in this section. 24.
PIC18(L)F1XK22 TABLE 24-1: OPCODE FIELD DESCRIPTIONS Field Description a RAM access bit a = 0: RAM location in Access RAM (BSR register is ignored) a = 1: RAM bank is specified by BSR register bbb Bit address within an 8-bit file register (0 to 7). BSR Bank Select Register. Used to select the current RAM bank. C, DC, Z, OV, N ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.
PIC18(L)F1XK22 FIGURE 24-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 15 10 9 8 7 OPCODE d a Example Instruction 0 f (FILE #) ADDWF MYREG, W, B d = 0 for result destination to be WREG register d = 1 for result destination to be file register (f) a = 0 to force Access Bank a = 1 for BSR to select bank f = 8-bit file register address Byte to Byte move operations (2-word) 15 12 11 OPCODE 15 0 f (Source FILE #) 12 11 MOVFF MYREG1, MYREG2 0 f (Destination FILE #) 1111 f =
PIC18(L)F1XK22 TABLE 24-2: PIC18FXXXX INSTRUCTION SET 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED OPERATIONS ADDWF ADDWFC ANDWF CLRF COMF CPFSEQ CPFSGT CPFSLT DECF DECFSZ DCFSNZ INCF INCFSZ INFSNZ IORWF MOVF MOVFF f, d, a f, d, a f, d, a f, a f, d, a f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a f, d, a fs, fd MOVWF MULWF NEGF RLCF RLNCF RRCF RRNCF SETF SUBFWB f, a f, a f, a f, d, a f, d, a f, d, a f, d, a f, a
PIC18(L)F1XK22 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes BIT-ORIENTED OPERATIONS BCF BSF BTFSC BTFSS BTG f, b, a f, b, a f, b, a f, b, a f, b, a Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set Bit Toggle f 1 1 1 (2 or 3) 1 (2 or 3) 1 1001 1000 1011 1010 0111 bbba bbba bbba bbba bbba ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff None None None None None 1 (2) 1 (2)
PIC18(L)F1XK22 TABLE 24-2: PIC18FXXXX INSTRUCTION SET (CONTINUED) 16-Bit Instruction Word Mnemonic, Operands Description Cycles MSb LSb Status Affected Notes LITERAL OPERATIONS ADDLW ANDLW IORLW LFSR k k k f, k MOVLB MOVLW MULLW RETLW SUBLW XORLW k k k k k k Add literal and WREG AND literal with WREG Inclusive OR literal with WREG Move literal (12-bit) 2nd word to FSR(f) 1st word Move literal to BSR<3:0> Move literal to WREG Multiply literal with WREG Return with literal in WREG Subtract WREG fr
PIC18(L)F1XK22 24.1.1 STANDARD INSTRUCTION SET ADDLW ADD literal to W ADDWF ADD W to f Syntax: ADDLW Syntax: ADDWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) + (f) dest Status Affected: N, OV, C, DC, Z k Operands: 0 k 255 Operation: (W) + k W Status Affected: N, OV, C, DC, Z Encoding: 0000 1111 kkkk kkkk Description: The contents of W are added to the 8-bit literal ‘k’ and the result is placed in W.
PIC18(L)F1XK22 ADDWFC ADD W and CARRY bit to f ANDLW Syntax: ADDWFC Syntax: ANDLW Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 k 255 Operation: (W) .AND. k W Status Affected: N, Z f {,d {,a}} Operation: (W) + (f) + (C) dest Status Affected: N,OV, C, DC, Z Encoding: 0010 Description: 00da Encoding: ffff ffff Add W, the CARRY flag and data memory location ‘f’. If ‘d’ is ‘0’, the result is placed in W. If ‘d’ is ‘1’, the result is placed in data memory location ‘f’.
PIC18(L)F1XK22 ANDWF AND W with f BC Branch if Carry Syntax: ANDWF Syntax: BC Operands: 0 f 255 d [0,1] a [0,1] Operands: -128 n 127 Operation: if CARRY bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f {,d {,a}} Operation: (W) .AND. (f) dest Status Affected: N, Z Encoding: 0001 Description: Encoding: 01da ffff ffff The contents of W are AND’ed with register ‘f’. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F1XK22 BCF Bit Clear f BN Branch if Negative Syntax: BCF Syntax: BN Operands: 0 f 255 0b7 a [0,1] Operands: -128 n 127 Operation: if NEGATIVE bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None f, b {,a} Operation: 0 f Status Affected: None Encoding: Encoding: 1001 Description: bbba ffff ffff Bit ‘b’ in register ‘f’ is cleared. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18(L)F1XK22 BNC Branch if Not Carry BNN Branch if Not Negative Syntax: BNC Syntax: BNN Operands: -128 n 127 Operands: -128 n 127 Operation: if CARRY bit is ‘0’ (PC) + 2 + 2n PC Operation: if NEGATIVE bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0011 nnnn nnnn Encoding: 1110 If the CARRY bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F1XK22 BNOV Branch if Not Overflow BNZ Branch if Not Zero Syntax: BNOV Syntax: BNZ Operands: -128 n 127 Operands: -128 n 127 Operation: if OVERFLOW bit is ‘0’ (PC) + 2 + 2n PC Operation: if ZERO bit is ‘0’ (PC) + 2 + 2n PC Status Affected: None Status Affected: None Encoding: n 1110 Description: 0101 nnnn nnnn Encoding: 1110 If the OVERFLOW bit is ‘0’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F1XK22 BRA Unconditional Branch BSF Syntax: BRA Syntax: BSF Operands: -1024 n 1023 Operands: 0 f 255 0b7 a [0,1] n Operation: (PC) + 2 + 2n PC Status Affected: None Encoding: 1101 Description: 0nnn nnnn nnnn Add the 2’s complement number ‘2n’ to the PC. Since the PC will have incremented to fetch the next instruction, the new address will be PC + 2 + 2n. This instruction is a 2-cycle instruction.
PIC18(L)F1XK22 BTFSC Bit Test File, Skip if Clear BTFSS Syntax: BTFSC f, b {,a} Syntax: BTFSS f, b {,a} Operands: 0 f 255 0b7 a [0,1] Operands: 0 f 255 0b<7 a [0,1] Operation: skip if (f) = 0 Operation: skip if (f) = 1 Status Affected: None Status Affected: None Encoding: 1011 bbba ffff ffff Bit Test File, Skip if Set Encoding: 1010 bbba ffff ffff Description: If bit ‘b’ in register ‘f’ is ‘0’, then the next instruction is skipped.
PIC18(L)F1XK22 BTG Bit Toggle f BOV Branch if Overflow Syntax: BTG f, b {,a} Syntax: BOV Operands: 0 f 255 0b<7 a [0,1] Operands: -128 n 127 Operation: if OVERFLOW bit is ‘1’ (PC) + 2 + 2n PC Status Affected: None Operation: (f) f Status Affected: None Encoding: 0111 Description: Words: Cycles: Encoding: bbba ffff ffff Bit ‘b’ in data memory location ‘f’ is inverted. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F1XK22 BZ Branch if Zero CALL Subroutine Call Syntax: BZ Syntax: CALL k {,s} Operands: -128 n 127 Operands: Operation: if ZERO bit is ‘1’ (PC) + 2 + 2n PC 0 k 1048575 s [0,1] Operation: (PC) + 4 TOS, k PC<20:1>, if s = 1 (W) WS, (Status) STATUSS, (BSR) BSRS Status Affected: None Status Affected: n None Encoding: 1110 Description: 0000 nnnn nnnn If the ZERO bit is ‘1’, then the program will branch. The 2’s complement number ‘2n’ is added to the PC.
PIC18(L)F1XK22 CLRF Clear f Syntax: CLRF Operands: 0 f 255 a [0,1] Operation: 000h f 1Z Status Affected: Z Encoding: f {,a} 0110 Description: 101a ffff ffff Clears the contents of the specified register. If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default). If ‘a’ is ‘0’ and the extended instruction set is enabled, this instruction operates in Indexed Literal Offset Addressing mode whenever f 95 (5Fh). See Section 24.2.
PIC18(L)F1XK22 COMF Complement f CPFSEQ Compare f with W, skip if f = W Syntax: COMF Syntax: CPFSEQ Operands: 0 f 255 a [0,1] Operation: (f) – (W), skip if (f) = (W) (unsigned comparison) Status Affected: None f {,d {,a}} 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) dest Status Affected: N, Z Encoding: 0001 11da ffff ffff Description: The contents of register ‘f’ are complemented. If ‘d’ is ‘0’, the result is stored in W.
PIC18(L)F1XK22 CPFSGT Compare f with W, skip if f > W CPFSLT Compare f with W, skip if f < W Syntax: CPFSGT Syntax: CPFSLT Operands: 0 f 255 a [0,1] Operands: 0 f 255 a [0,1] Operation: (f) –W), skip if (f) > (W) (unsigned comparison) Operation: (f) –W), skip if (f) < (W) (unsigned comparison) Status Affected: None Status Affected: None Encoding: 0110 Description: Words: f {,a} 010a ffff ffff Compares the contents of data memory location ‘f’ to the contents of the
PIC18(L)F1XK22 DAW Decimal Adjust W Register DECF Syntax: DAW Syntax: DECF f {,d {,a}} Operands: None Operands: Operation: If [W<3:0> > 9] or [DC = 1] then (W<3:0>) + 6 W<3:0>; else (W<3:0>) W<3:0>; 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest Status Affected: C, DC, N, OV, Z If [W<7:4> + DC > 9] or [C = 1] then (W<7:4>) + 6 + DC W<7:4>; else (W<7:4>) + DC W<7:4> Status Affected: Decrement f Encoding: 0000 0000 0000 0000 0111 Description: DAW adjusts the 8-bit
PIC18(L)F1XK22 DECFSZ Decrement f, skip if 0 DCFSNZ Syntax: DECFSZ f {,d {,a}} Syntax: DCFSNZ Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – 1 dest, skip if result = 0 Operation: (f) – 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0010 Description: 11da ffff ffff The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F1XK22 GOTO Unconditional Branch INCF Syntax: GOTO k Syntax: INCF Operands: 0 k 1048575 Operands: Operation: k PC<20:1> Status Affected: None 0 f 255 d [0,1] a [0,1] Operation: (f) + 1 dest Status Affected: C, DC, N, OV, Z Encoding: 1st word (k<7:0>) 2nd word(k<19:8>) Description: 1110 1111 1111 k19kkk k7kkk kkkk kkkk0 kkkk8 GOTO allows an unconditional branch Increment f Encoding: 0010 2 Cycles: 2 Q1 Q2 Q3 Q4 Read literal ‘k’<7:0>, No operation Re
PIC18(L)F1XK22 INCFSZ Increment f, skip if 0 INFSNZ Syntax: INCFSZ Syntax: INFSNZ 0 f 255 d [0,1] a [0,1] f {,d {,a}} Increment f, skip if not 0 f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: Operation: (f) + 1 dest, skip if result = 0 Operation: (f) + 1 dest, skip if result 0 Status Affected: None Status Affected: None Encoding: 0011 Description: 11da ffff ffff The contents of register ‘f’ are incremented. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F1XK22 IORLW Inclusive OR literal with W IORWF Syntax: IORLW k Syntax: IORWF Operands: 0 k 255 Operands: Operation: (W) .OR. k W Status Affected: N, Z 0 f 255 d [0,1] a [0,1] Operation: (W) .OR. (f) dest Status Affected: N, Z Encoding: 0000 Description: 1001 kkkk kkkk The contents of W are ORed with the 8bit literal ‘k’. The result is placed in W.
PIC18(L)F1XK22 LFSR Load FSR MOVF Syntax: LFSR f, k Syntax: MOVF Operands: 0f2 0 k 4095 Operands: Operation: k FSRf 0 f 255 d [0,1] a [0,1] Status Affected: None Operation: f dest Status Affected: N, Z Encoding: 1110 1111 1110 0000 00ff k7kkk k11kkk kkkk Description: The 12-bit literal ‘k’ is loaded into the File Select Register pointed to by ‘f’.
PIC18(L)F1XK22 MOVFF Move f to f MOVLB Syntax: MOVFF fs,fd Syntax: MOVLB k Operands: 0 fs 4095 0 fd 4095 Operands: 0 k 255 Operation: k BSR Operation: (fs) fd Status Affected: None Status Affected: None Encoding: Encoding: 1st word (source) 2nd word (destin.) Description: 1100 1111 ffff ffff ffff ffff ffffs ffffd The contents of source register ‘fs’ are moved to destination register ‘fd’.
PIC18(L)F1XK22 MOVLW Move literal to W MOVWF Syntax: MOVLW k Syntax: MOVWF Operands: 0 k 255 Operands: Operation: kW 0 f 255 a [0,1] Status Affected: None Operation: (W) f Status Affected: None Encoding: 0000 1110 kkkk kkkk Description: The 8-bit literal ‘k’ is loaded into W. Words: 1 Cycles: 1 Move W to f Encoding: 0110 Q1 Q2 Q3 Q4 Read literal ‘k’ Process Data Write to W Example: MOVLW = ffff ffff Move data from W to register ‘f’.
PIC18(L)F1XK22 MULLW Multiply literal with W MULWF Multiply W with f Syntax: MULLW Syntax: MULWF Operands: 0 k 255 Operands: Operation: (W) x k PRODH:PRODL 0 f 255 a [0,1] Status Affected: None Operation: (W) x (f) PRODH:PRODL Status Affected: None Encoding: 0000 Description: k 1101 kkkk kkkk An unsigned multiplication is carried out between the contents of W and the 8-bit literal ‘k’. The 16-bit result is placed in the PRODH:PRODL register pair.
PIC18(L)F1XK22 NEGF Negate f NOP No Operation Syntax: NEGF Syntax: NOP Operands: 0 f 255 a [0,1] Operands: None Operation: (f)+1f Status Affected: N, OV, C, DC, Z Encoding: f {,a} 0110 Description: 1 Cycles: 1 No operation Status Affected: None Encoding: 110a ffff 0000 1111 ffff Location ‘f’ is negated using two’s complement. The result is placed in the data memory location ‘f’. If ‘a’ is ‘0’, the Access Bank is selected.
PIC18(L)F1XK22 POP Pop Top of Return Stack PUSH Push Top of Return Stack Syntax: POP Syntax: PUSH Operands: None Operands: None Operation: (TOS) bit bucket Operation: (PC + 2) TOS Status Affected: None Status Affected: None Encoding: 0000 0000 0000 0110 Description: The TOS value is pulled off the return stack and is discarded. The TOS value then becomes the previous value that was pushed onto the return stack.
PIC18(L)F1XK22 RCALL Relative Call RESET Reset Syntax: RCALL Syntax: RESET Operands: -1024 n 1023 Operands: None Operation: (PC) + 2 TOS, (PC) + 2 + 2n PC Operation: Reset all registers and flags that are affected by a MCLR Reset. Status Affected: None Status Affected: All Encoding: n 1101 Description: 1nnn nnnn nnnn Subroutine call with a jump up to 1K from the current location. First, return address (PC + 2) is pushed onto the stack.
PIC18(L)F1XK22 RETFIE Return from Interrupt RETLW Return literal to W Syntax: RETFIE {s} Syntax: RETLW k Operands: s [0,1] Operands: 0 k 255 Operation: (TOS) PC, 1 GIE/GIEH or PEIE/GIEL, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged.
PIC18(L)F1XK22 RETURN Return from Subroutine RLCF Syntax: RETURN {s} Syntax: RLCF Operands: s [0,1] Operands: Operation: (TOS) PC, if s = 1 (WS) W, (STATUSS) Status, (BSRS) BSR, PCLATU, PCLATH are unchanged 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) C, (C) dest<0> Status Affected: C, N, Z Status Affected: None Encoding: 0000 Rotate Left f through Carry Encoding: 0000 0001 001s Description: Return from subroutine.
PIC18(L)F1XK22 RLNCF Rotate Left f (No Carry) RRCF Syntax: RLNCF Syntax: RRCF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) dest, (f<7>) dest<0> Operation: Status Affected: N, Z (f) dest, (f<0>) C, (C) dest<7> Status Affected: C, N, Z Encoding: 0100 Description: f {,d {,a}} 01da ffff ffff The contents of register ‘f’ are rotated one bit to the left. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F1XK22 RRNCF Rotate Right f (No Carry) SETF Syntax: RRNCF Syntax: SETF Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 a [0,1] Operation: FFh f Operation: (f) dest, (f<0>) dest<7> Status Affected: None Status Affected: f {,d {,a}} Encoding: N, Z Encoding: 0100 Description: 00da ffff ffff The contents of register ‘f’ are rotated one bit to the right. If ‘d’ is ‘0’, the result is placed in W.
PIC18(L)F1XK22 SLEEP Enter Sleep mode SUBFWB Syntax: SLEEP Syntax: SUBFWB Operands: None Operands: Operation: 00h WDT, 0 WDT postscaler, 1 TO, 0 PD 0 f 255 d [0,1] a [0,1] Operation: (W) – (f) – (C) dest Status Affected: N, OV, C, DC, Z Status Affected: TO, PD Encoding: 0000 Encoding: 0000 0000 0011 Description: The Power-down Status bit (PD) is cleared. The Time-out Status bit (TO) is set. Watchdog Timer and its postscaler are cleared.
PIC18(L)F1XK22 SUBLW Subtract W from literal SUBWF Syntax: SUBLW k Syntax: SUBWF Operands: 0 k 255 Operands: Operation: k – (W) W Status Affected: N, OV, C, DC, Z 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) dest Status Affected: N, OV, C, DC, Z Encoding: 0000 Description 1000 kkkk kkkk W is subtracted from the 8-bit literal ‘k’. The result is placed in W.
PIC18(L)F1XK22 SUBWFB Subtract W from f with Borrow SWAPF Swap f Syntax: SUBWFB Syntax: SWAPF f {,d {,a}} Operands: 0 f 255 d [0,1] a [0,1] Operands: 0 f 255 d [0,1] a [0,1] Operation: (f) – (W) – (C) dest Operation: Status Affected: N, OV, C, DC, Z (f<3:0>) dest<7:4>, (f<7:4>) dest<3:0> Status Affected: None Encoding: 0101 Description: f {,d {,a}} 10da ffff ffff Subtract W and the CARRY flag (borrow) from register ‘f’ (2’s complement method).
PIC18(L)F1XK22 TBLRD Table Read TBLRD Table Read (Continued) Syntax: TBLRD ( *; *+; *-; +*) Example1: TBLRD Operands: None Operation: if TBLRD *, (Prog Mem (TBLPTR)) TABLAT; TBLPTR – No Change; if TBLRD *+, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) + 1 TBLPTR; if TBLRD *-, (Prog Mem (TBLPTR)) TABLAT; (TBLPTR) – 1 TBLPTR; if TBLRD +*, (TBLPTR) + 1 TBLPTR; (Prog Mem (TBLPTR)) TABLAT; Example2: 0000 0000 0000 TBLRD = = = 55h 00A356h 34h = = 34h 00A357h +* ; Before Instruction TAB
PIC18(L)F1XK22 TBLWT Table Write TBLWT Table Write (Continued) Syntax: TBLWT ( *; *+; *-; +*) Example1: TBLWT *+; Operands: None Operation: if TBLWT*, (TABLAT) Holding Register; TBLPTR – No Change; if TBLWT*+, (TABLAT) Holding Register; (TBLPTR) + 1 TBLPTR; if TBLWT*-, (TABLAT) Holding Register; (TBLPTR) – 1 TBLPTR; if TBLWT+*, (TBLPTR) + 1 TBLPTR; (TABLAT) Holding Register; Status Affected: Before Instruction TABLAT = 55h TBLPTR = 00A356h HOLDING REGISTER (00A356h) = FFh After In
PIC18(L)F1XK22 TSTFSZ Test f, skip if 0 XORLW Syntax: TSTFSZ f {,a} Syntax: XORLW k Operands: 0 f 255 a [0,1] Operands: 0 k 255 Operation: (W) .XOR. k W Operation: skip if f = 0 Status Affected: N, Z Status Affected: None Encoding: Encoding: 0110 Description: Exclusive OR literal with W 011a ffff ffff If ‘f’ = 0, the next instruction fetched during the current instruction execution is discarded and a NOP is executed, making this a 2-cycle instruction.
PIC18(L)F1XK22 XORWF Exclusive OR W with f Syntax: XORWF Operands: 0 f 255 d [0,1] a [0,1] Operation: (W) .XOR. (f) dest Status Affected: N, Z Encoding: 0001 f {,d {,a}} 10da ffff ffff Description: Exclusive OR the contents of W with register ‘f’. If ‘d’ is ‘0’, the result is stored in W. If ‘d’ is ‘1’, the result is stored back in the register ‘f’ (default). If ‘a’ is ‘0’, the Access Bank is selected. If ‘a’ is ‘1’, the BSR is used to select the GPR bank (default).
PIC18(L)F1XK22 24.2 A summary of the instructions in the extended instruction set is provided in Table 24-3. Detailed descriptions are provided in Section 24.2.2 “Extended Instruction Set”. The opcode field descriptions in Table 24-1 (page 266) apply to both the standard and extended PIC18 instruction sets. Extended Instruction Set In addition to the standard 75 instructions of the PIC18 instruction set, PIC18(L)F1XK22 devices also provide an optional extension to the core CPU functionality.
PIC18(L)F1XK22 24.2.2 EXTENDED INSTRUCTION SET ADDFSR Add Literal to FSR ADDULNK Syntax: ADDFSR f, k Syntax: ADDULNK k Operands: 0 k 63 f [ 0, 1, 2 ] Operands: 0 k 63 Operation: FSR(f) + k FSR(f) Status Affected: None Encoding: 1110 Add Literal to FSR2 and Return FSR2 + k FSR2, Operation: (TOS) PC Status Affected: 1000 ffkk kkkk Description: The 6-bit literal ‘k’ is added to the contents of the FSR specified by ‘f’.
PIC18(L)F1XK22 CALLW Subroutine Call Using WREG MOVSF Syntax: CALLW Syntax: MOVSF [zs], fd Operands: None Operands: Operation: (PC + 2) TOS, (W) PCL, (PCLATH) PCH, (PCLATU) PCU 0 zs 127 0 fd 4095 Operation: ((FSR2) + zs) fd Status Affected: None Status Affected: None Encoding: 0000 0000 0001 0100 Description First, the return address (PC + 2) is pushed onto the return stack. Next, the contents of W are written to PCL; the existing value is discarded.
PIC18(L)F1XK22 MOVSS Move Indexed to Indexed PUSHL Syntax: Syntax: PUSHL k Operands: MOVSS [zs], [zd] 0 zs 127 0 zd 127 Operands: 0k 255 Operation: ((FSR2) + zs) ((FSR2) + zd) Operation: k (FSR2), FSR2 – 1 FSR2 Status Affected: None Status Affected: None Encoding: 1st word (source) 2nd word (dest.) Description 1110 1111 1011 xxxx 1zzz xzzz zzzzs zzzzd The contents of the source register are moved to the destination register.
PIC18(L)F1XK22 SUBFSR Subtract Literal from FSR SUBULNK Syntax: SUBFSR f, k Syntax: SUBULNK k Operands: 0 k 63 Operands: 0 k 63 f [ 0, 1, 2 ] Operation: Operation: FSR(f) – k FSRf Status Affected: None Encoding: 1110 FSR2 – k FSR2 (TOS) PC Status Affected: None 1001 ffkk kkkk Description: The 6-bit literal ‘k’ is subtracted from the contents of the FSR specified by ‘f’.
PIC18(L)F1XK22 24.2.3 Note: BYTE-ORIENTED AND BIT-ORIENTED INSTRUCTIONS IN INDEXED LITERAL OFFSET MODE Enabling the PIC18 instruction set extension may cause legacy applications to behave erratically or fail entirely. In addition to eight new commands in the extended set, enabling the extended instruction set also enables Indexed Literal Offset Addressing mode (Section 3.5.1 “Indexed Addressing with Literal Offset”).
PIC18(L)F1XK22 ADDWF ADD W to Indexed (Indexed Literal Offset mode) BSF Bit Set Indexed (Indexed Literal Offset mode) Syntax: ADDWF Syntax: BSF [k], b Operands: 0 k 95 d [0,1] Operands: 0 f 95 0b7 Operation: (W) + ((FSR2) + k) dest Operation: 1 ((FSR2) + k) Status Affected: N, OV, C, DC, Z Status Affected: None Encoding: [k] {,d} 0010 Description: 01d0 kkkk kkkk The contents of W are added to the contents of the register indicated by FSR2, offset by the value ‘k
PIC18(L)F1XK22 24.2.5 SPECIAL CONSIDERATIONS WITH MICROCHIP MPLAB® IDE TOOLS The latest versions of Microchip’s software tools have been designed to fully support the extended instruction set of the PIC18(L)F1XK22 family of devices. This includes the MPLAB® C18 C compiler, MPASM assembly language and MPLAB Integrated Development Environment (IDE). When selecting a target device for software development, MPLAB IDE will automatically set default Configuration bits for that device.
PIC18(L)F1XK22 25.
PIC18(L)F1XK22 25.2 MPLAB XC Compilers The MPLAB XC Compilers are complete ANSI C compilers for all of Microchip’s 8, 16, and 32-bit MCU and DSC devices. These compilers provide powerful integration capabilities, superior code optimization and ease of use. MPLAB XC Compilers run on Windows, Linux or MAC OS X. For easy source level debugging, the compilers provide debug information that is optimized to the MPLAB X IDE.
PIC18(L)F1XK22 25.6 MPLAB X SIM Software Simulator The MPLAB X SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis.
PIC18(L)F1XK22 25.11 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification.
PIC18(L)F1XK22 26.0 ELECTRICAL SPECIFICATIONS 26.1 Absolute Maximum Ratings(†) Ambient temperature under bias...................................................................................................... -40°C to +125°C Storage temperature ........................................................................................................................ -65°C to +150°C Voltage on pins with respect to VSS on VDD pin PIC18F1XK22 ................................................................
PIC18(L)F1XK22 26.2 Standard Operating Conditions The standard operating conditions for any device are defined as: Operating Voltage: Operating Temperature: VDDMIN VDD VDDMAX TA_MIN TA TA_MAX VDD — Operating Supply Voltage(1) PIC18LF1XK22 VDDMIN (Fosc 16 MHz).......................................................................................................... +1.8V VDDMIN (Fosc 20 MHz)........................................................................................................
PIC18(L)F1XK22 FIGURE 26-1: PIC18F1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C 5.5 VDD (V) 3.6 3.0 2.3 0 10 20 40 48 64 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies. FIGURE 26-2: PIC18F1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C 5.5 VDD (V) 3.6 3.0 2.
PIC18(L)F1XK22 FIGURE 26-3: PIC18LF1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +85°C VDD (V) 3.6 3.0 2.0 1.8 0 10 16 20 40 48 64 Frequency (MHz) Note 1: The shaded region indicates the permissible combinations of voltage and frequency. 2: Refer to Table 26-13 for each Oscillator mode’s supported frequencies. FIGURE 26-4: PIC18LF1XK22 VOLTAGE FREQUENCY GRAPH, -40°C TA +125°C VDD (V) 3.6 3.0 2.0 1.
PIC18(L)F1XK22 FIGURE 26-5: HFINTOSC FREQUENCY ACCURACY OVER DEVICE VDD AND TEMPERATURE 125 ± 5% Temperature (°C) 85 ± 3% 60 25 ± 2% 0 -20 -40 1.8 ± 5% 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 26.3 DC Characteristics TABLE 26-1: SUPPLY VOLTAGE PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. D001 Sym. VDD Characteristic VDR Max. Units Conditions PIC18LF1XK22 1.8 2.0 3.0 3.0 — — — — 3.6 3.6 3.6 3.6 V V V V FOSC 16 MHz FOSC 20 MHz FOSC 64 MHz 85°C FOSC 48 MHz 125°C PIC18F1XK22 2.3 3.0 3.0 — — — 5.5 5.5 5.
PIC18(L)F1XK22 FIGURE 26-6: POR AND POR REARM WITH SLOW RISING VDD VDD VPOR VPORR VSS NPOR POR REARM VSS TVLOW(2) Note 1: 2: 3: TPOR(3) When NPOR is low, the device is held in Reset. TPOR 1 s typical. TVLOW 2.7 s typical. 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 TABLE 26-2: RC RUN SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. D008 Device Characteristics Typ. Supply Current (IDD)(1, 2, 4, 5) D008A D008 D008A D008B Max.
PIC18(L)F1XK22 TABLE 26-3: RC IDLE SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. D011 Device Characteristics Typ. Max.
PIC18(L)F1XK22 TABLE 26-4: PRIMARY RUN SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Typ. Max. Units Supply Current (IDD)(1, 2, 4, 5) 0.20 0.32 mA -40°C to +125°C VDD = 1.8V 0.27 0.39 mA -40°C to +125°C VDD = 3.0V D014 .20 .32 mA -40°C to +125°C VDD = 2.3V D014A .27 .39 mA -40°C to +125°C VDD = 3.0V D014B .30 .
PIC18(L)F1XK22 TABLE 26-5: PRIMARY IDLE SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Typ. Max. Units Supply Current (IDD)(1, 2, 4, 5) 70 105 A -40°C to +125°C VDD = 1.8V 140 180 A -40°C to +125°C VDD = 3.0V D019 80 120 A -40°C to +125°C VDD = 2.3V D019A 140 180 A -40°C to +125°C VDD = 3.
PIC18(L)F1XK22 TABLE 26-6: SECONDARY RUN SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. D022 Device Characteristics Supply Current (IDD)(1, 2, 4) D022A D022 D022A D022B * Note 1: 2: 3: 4: Typ. Max.
PIC18(L)F1XK22 TABLE 26-7: SECONDARY IDLE SUPPLY CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. D023 Device Characteristics Supply Current (IDD)(1, 2, 4) D023A D023 D023A D023B * Note 1: 2: 3: 4: Typ. Max.
PIC18(L)F1XK22 TABLE 26-8: POWER-DOWN CURRENT PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Power-down Base Current Min. Typ.† Conditions Max. +85°C Max. +125°C Units VDD Note (IPD)(2) D027 D027 — 0.034 1.0 9.0 A 1.8 — 0.071 2.0 10 A 3.0 — 17 40 55 A 2.3 — 18 43 65 A 3.0 — 20 45 80 A 5.0 — .46 1.3 10 A 1.8 — .74 3.
PIC18(L)F1XK22 TABLE 26-8: POWER-DOWN CURRENT (CONTINUED) PIC18LF1XK22 Standard Operating Conditions (unless otherwise stated) PIC18F1XK22 Standard Operating Conditions (unless otherwise stated) Param. No. Device Characteristics Min. Conditions Max. +85°C Max. +125°C Units .7 1.0 9.0 A Typ.† VDD Note 1.8 A/D Current(1, 4), no conversion in progress Power-down Module Current D032 — — .8 3.0 10 A 3.0 D032 — 19 42 60 A 2.3 — 20 44 65 A 3.0 — 22 46 80 A 5.
PIC18(L)F1XK22 TABLE 26-9: I/O PORTS DC CHARACTERISTICS Param. No. Sym. VIL Characteristic Standard Operating Conditions (unless otherwise stated) Min. Typ.† Max. Units Conditions Input Low Voltage I/O ports: D036 with TTL buffer D036A D036B with Schmitt Trigger buffer D037 2 VSS — 0.8 V 4.5V VDD 5.5V VSS — 0.15 VDD V 1.8V VDD 4.5V VSS — 0.2 VDD V 2.0V VDD 5.5V VSS — 0.2 VDD V 1.8V VDD 5.5V D037A with I C levels VSS — 0.
PIC18(L)F1XK22 TABLE 26-9: I/O PORTS (CONTINUED) DC CHARACTERISTICS Param. No. Sym. VOL D080 Characteristic Standard Operating Conditions (unless otherwise stated) Min. Typ.† Max. Units — — VSS+0.6 VSS+0.6 VSS+0.6 V Output Low Voltage(4) I/O ports * † Note 1: 2: 3: 4: Conditions IOL = 8 mA, VDD = 5V IOL = 6 mA, VDD = 3.3V IOL = 3 mA, VDD = VDDMIN These parameters are characterized but not tested. Data in “Typ” column is at 3.0V, 25°C unless otherwise stated.
PIC18(L)F1XK22 TABLE 26-9: I/O PORTS (CONTINUED) DC CHARACTERISTICS Param. No. Sym. VOH D090 Characteristic Standard Operating Conditions (unless otherwise stated) Min. Typ.† Max. Units VDD-0.7 VDD-0.7 VDD-0.7 — — V — — 15 pF — — 50 pF Conditions Output High Voltage(4) I/O ports IOH = 3.5 mA, VDD = 5V IOH = 3 mA, VDD = 3.
PIC18(L)F1XK22 TABLE 26-10: MEMORY PROGRAMMING REQUIREMENTS DC CHARACTERISTICS Param. No. Sym. Standard Operating Conditions (unless otherwise stated) Characteristic Min. Typ.† Max.
PIC18(L)F1XK22 TABLE 26-11: THERMAL CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Param. No. TH01 TH02 Sym. JA JC Characteristic Typ. Units Thermal Resistance Junction to Ambient 62.2 C/W 20-pin PDIP package 75.0 C/W 20-pin SOIC package 89.3 C/W 20-pin SSOP package 43.0 C/W 20-pin QFN 4x4mm package 27.5 C/W 20-pin PDIP package 23.1 C/W 20-pin SOIC package 31.1 C/W 20-pin SSOP package 5.
PIC18(L)F1XK22 26.4 Timing Parameter Symbology The timing parameter symbols have been created with one of the following formats: 1. TppS2ppS 2.
PIC18(L)F1XK22 26.5 AC Characteristics: PIC18(L)F1XK22-I/E FIGURE 26-8: CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1/CLKIN OS02 OS04 OS04 OS03 OSC2/CLKOUT (LP,XT,HS Modes) OSC2/CLKOUT (CLKOUT Mode) DS40001365F-page 340 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 TABLE 26-12: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. 1A Symbol FOSC Characteristic External CLKIN Frequency(1) Oscillator Frequency(1) 1 TOSC External CLKIN Period(1) Oscillator Period(1) Time(1) 2 TCY Instruction Cycle 3 TOSL, TOSH External Clock in (OSC1) High or Low Time 4 Note 1: TOSR, TOSF External Clock in (OSC1) Rise or Fall Time Min. Max.
PIC18(L)F1XK22 TABLE 26-13: OSCILLATOR PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. OS08 Sym. HFOSC OS09 OS10* LFOSC Characteristic Internal Calibrated HFINTOSC Frequency(2) Internal LFINTOSC Frequency TIOSC ST HFINTOSC Wake-up from Sleep Start-up Time Freq. Tolerance Min. Typ.† Max. Units 2% 3% — — 16.0 16.0 — — MHz MHz 5% — 16.0 — MHz 0 — 31.25 — kHz — — 5 8 s VDD = 2.0V, -40°C to +85°C — — 5 8 s VDD = 3.
PIC18(L)F1XK22 FIGURE 26-9: Cycle CLKOUT AND I/O TIMING Write Fetch Read Execute Q4 Q1 Q2 Q3 FOSC OS12 OS11 OS20 OS21 CLKOUT OS19 OS18 OS16 OS13 OS17 I/O pin (Input) OS14 OS15 I/O pin (Output) New Value Old Value OS18, OS19 TABLE 26-15: CLKOUT AND I/O TIMING PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions OS11 TOSH2CKL Fosc to CLKOUT (1) — — 70 ns VDD = 3.3-5.
PIC18(L)F1XK22 FIGURE 26-10: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Start-Up Time Internal Reset(1) Watchdog Timer Reset(1) 31/ 31A 34 34 I/O pins Note 1: Asserted low.
PIC18(L)F1XK22 TABLE 26-16: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET PARAMETERS Standard Operating Conditions (unless otherwise stated) Param. No. Sym. Characteristic Min. Typ.† Max. Units Conditions 30 TMCL MCLR Pulse Width (low) 2 5 — — — — s s VDD = 3.3-5V, -40°C to +85°C VDD = 3.3-5V 31 TWDT Standard Watchdog Timer Time-out Period (1:16 Prescaler) 10 10 17 17 27 30 ms ms VDD = 3.3V-5V, -40°C to +85°C VDD = 3.
PIC18(L)F1XK22 FIGURE 26-12: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS T0CKI 40 41 42 T1CKI 45 46 49 47 TMR0 or TMR1 TABLE 26-17: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. 40* Sym. TT0H Characteristic Min. Typ.† Max. Units 0.5 TCY + 20 — — ns 10 — — ns 0.5 TCY + 20 — — ns 10 — — ns Greater of: 20 or TCY + 40 N — — ns 0.5 TCY + 20 — — ns 15 — — ns 30 — — ns Synchronous, No Prescaler 0.
PIC18(L)F1XK22 FIGURE 26-13: CAPTURE/COMPARE/PWM TIMINGS (CCP) CCPx (Capture mode) CC01 CC02 CC03 Note: Refer to Figure 26-7 for load conditions. TABLE 26-18: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP) Standard Operating Conditions (unless otherwise stated) Param. No. Sym. CC01* TccL Characteristic CCPx Input Low Time No Prescaler Min. Typ.† Max. Units 0.5TCY + 20 — — ns 20 — — ns 0.
PIC18(L)F1XK22 FIGURE 26-14: A/D CONVERSION TIMING BSF ADCON0, GO (Note 2) 131 Q4 130 132 A/D CLK 9 A/D DATA 8 7 .. . ... 2 1 0 NEW_DATA OLD_DATA ADRES TCY ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 2: This is a minimal RC delay (typically 100 ns), which also disconnects the holding capacitor from the analog input.
PIC18(L)F1XK22 TABLE 26-21: COMPARATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated) Param. No. CM01 Sym. Characteristics VICM Input Common-mode Voltage CM04 TRESP Response Time * Note 1: Typ. Max. Units — 10 50 mV VREF = VDD/2, High-Power mode — 12 80 mV VREF = VDD/2, Low-Power mode VSS — VDD V — 200 400 ns High-Power mode — 300 600 ns Low-Power mode — — 10 s Input Offset Voltage VIOFF CM02 CM05 Min.
PIC18(L)F1XK22 FIGURE 26-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING CK US121 US121 DT US122 US120 Note: Refer to Figure 26-7 for load conditions. TABLE 26-24: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Standard Operating Conditions (unless otherwise stated) Param. No. Symbol Characteristic Min. Max. Units US120 TCKH2DTV SYNC XMIT (Master and Slave) Clock high to data-out valid 3.0-5.5V — 80 ns 1.8-5.5V — 100 ns Clock out rise time and fall time (Master mode) 3.0-5.
PIC18(L)F1XK22 FIGURE 26-17: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS SP70 SCK (CKP = 0) SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 bit 6 - - - - - -1 MSb SDO LSb SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 26-7 for load conditions.
PIC18(L)F1XK22 FIGURE 26-19: SPI SLAVE MODE TIMING (CKE = 0) SS SP70 SCK (CKP = 0) SP83 SP71 SP72 SP78 SP79 SP79 SP78 SCK (CKP = 1) SP80 MSb SDO LSb bit 6 - - - - - -1 SP77 SP75, SP76 SDI MSb In bit 6 - - - -1 LSb In SP74 SP73 Note: Refer to Figure 26-7 for load conditions.
PIC18(L)F1XK22 TABLE 26-26: SPI MODE REQUIREMENTS Param. No. Symbol Characteristic SP70* TSSL2SCH, TSSL2SCL SS to SCK or SCK input SP71* TSCH Min. Typ.† Max.
PIC18(L)F1XK22 TABLE 26-27: I2C BUS START/STOP BITS REQUIREMENTS Param. No. Symbol SP90* TSU:STA SP91* THD:STA SP92* TSU:STO SP93 THD:STO Stop condition Characteristic Start condition 100 kHz mode 4700 Typ. Max. Units — — Setup time 400 kHz mode 600 — — Start condition 100 kHz mode 4000 — — Hold time 400 kHz mode 600 — — Stop condition 100 kHz mode 4700 — — Setup time Hold time * Min.
PIC18(L)F1XK22 TABLE 26-28: I2C BUS DATA REQUIREMENTS Param. No. Symbol SP100* THIGH Characteristic Clock high time Min. Max. Units Conditions 100 kHz mode 4.0 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 0.6 — s Device must operate at a minimum of 10 MHz 1.5TCY — 100 kHz mode 4.7 — s Device must operate at a minimum of 1.5 MHz 400 kHz mode 1.3 — s Device must operate at a minimum of 10 MHz 1.
PIC18(L)F1XK22 27.0 DC AND AC CHARACTERISTICS GRAPHS AND CHARTS The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables, the data presented are outside specified operating range (i.e., outside specified VDD range). This is for information only and devices are ensured to operate properly only within the specified range.
PIC18(L)F1XK22 FIGURE 27-1: PIC18LF1XK22 TYPICAL BASE IPD 5 4.5 4 125°C 3.5 IPD (uA) 3 2.5 2 1.5 1 85°C 25°C -40°C 0.5 0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) FIGURE 27-2: PIC18LF1XK22 TYPICAL IPD FOR WATCHDOG TIMER 6.0 5.4 125°C 4.8 IPD (uA) 4.2 3.6 3.0 2.4 1.8 85°C 1.2 Typ. 25°C 0.6 0.0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-3: PIC18LF1XK22 TYPICAL IPD FOR BROWN-OUT RESET 16 14 125°C 12 10 IPD (uA) 85°C 8 Typ. 25°C 6 4 2 0 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 3 VDD (V) FIGURE 27-4: PIC18LF1XK22 TYPICAL IPD FOR DIGITAL-TO-ANALOG CONVERTER (CVREF) 40 35 30 25 IPD (uA) 125°C 85°C 20 25°C 15 10 5 0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) DS40001365F-page 358 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-5: PIC18LF1XK22 ICOMP – TYPICAL IPD FOR COMPARATOR IN LOW-POWER MODE 25.0 IPD (uA) 20.0 15.0 125°C 85°C 10.0 25°C -40°C 5.0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) FIGURE 27-6: PIC18LF1XK22 ICOMP – TYPICAL IPD FOR COMPARATOR IN HIGH-POWER MODE 125 100 75 IPD (uA) 125°C 85°C 25°C 50 -40°C 25 0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-7: PIC18LF1XK22 TYPICAL RC_RUN 31 kHz IDD 30 25 IDD (uA) 20 15 125°C 85°C 10 25°C -40°C 5 0 1.8 2 2.2 2.4 2.6 2.8 3 2.6 2.8 3 VDD (V) FIGURE 27-8: PIC18LF1XK22 TYPICAL RC_RUN IDD 5.0 4.5 4.0 IDD (mA) 3.5 3.0 16 MHz 2.5 2.0 1.5 1.0 1 MHz 0.5 0.0 1.8 2 2.2 2.4 VDD (V) DS40001365F-page 360 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-9: PIC18LF1XK22 TYPICAL PRI_RUN IDD (EC) 4.0 3.5 3.0 16 MHz IDD (mA) 2.5 2.0 1.5 1.0 0.5 1 MHz 0.0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) FIGURE 27-10: PIC18LF1XK22 TYPICAL PRI_RUN IDD (HS + PLL) 5.0 4.5 4.0 3.5 IDD (mA) 3.0 16 MHz (4 MHz Input) 2.5 2.0 1.5 1.0 0.5 0.0 1.8 2 2.2 2.4 2.6 2.8 3 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-11: MEMLOW TYPICAL BASE IPD 50 45 40 35 125°C IPD (uA) 30 25 85°C 20 25°C 15 -40°C 10 5 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) FIGURE 27-12: MEMLOW TYPICAL IPD FOR WATCHDOG TIMER 40.0 35.0 125°C 30.0 85°C IPD (uA) 25.0 Typ. 25°C 20.0 15.0 15 0 10.0 5.0 0.0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) DS40001365F-page 362 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-13: MEMLOW TYPICAL IPD FOR BROWN-OUT RESET 80 70 60 125°C 85°C IPD (uA) 50 Typ. 25°C 40 30 20 10 0 3 3.2 3.4 3.6 3.8 4 4.2 4.4 4.6 4.8 5 VDD (V) FIGURE 27-14: MEMLOW TYPICAL IPD FOR DIGITAL-TO-ANALOG CONVERTER (CVREF) 80 70 60 125°C 85°C IPD (uA) 50 25°C 40 30 20 10 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-15: MEMLOW ICOMP – TYPICAL IPD FOR COMPARATOR IN LOW-POWER MODE 60.0 55.0 50.0 45.0 125°C IPD (uA) 40.0 85°C 35.0 25°C 30.0 -40°C 25.0 20.0 15.0 10.0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) FIGURE 27-16: MEMLOW ICOMP – TYPICAL IPD FOR COMPARATOR IN HIGH-POWER MODE 150 125 125°C 100 85°C IPD (uA) 25°C 75 -40°C 50 25 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) DS40001365F-page 364 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-17: MEMLOW TYPICAL RC_RUN 31 kHz IDD 50 45 40 125°C IDD (uA) 35 85°C 25°C 30 -40°C 25 20 15 10 5 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) FIGURE 27-18: MEMLOW TYPICAL RC_RUN IDD 5.0 4.5 4.0 16 MHz 3.5 IDD (mA) 3.0 2.5 2.0 1.5 1.0 1 MHz 0.5 0.0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-19: MEMLOW TYPICAL PRI_RUN IDD (EC) 14 64 MHz 12 10 IDD (mA) 8 6 4 16 MHz 2 1 MHz 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) FIGURE 27-20: MEMLOW TYPICAL PRI_RUN IDD (HS + PLL) 16 14 64 MHz (16 MHz Input) 12 IDD (mA) 10 8 6 4 16 MHz (4 MHz Input) 2 0 2.3 2.8 3.3 3.8 4.3 4.8 VDD (V) DS40001365F-page 366 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-21: PIC18(L)F1XK22 TTL BUFFER TYPICAL VIH 2.1 1.9 Min. 1.7 1.5 -40°C VIH (V) 1.3 25°C 1.1 85°C 125°C 0.9 0.7 0.5 0.3 0.1 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VDD (V) FIGURE 27-22: PIC18(L)F1XK22 SCHMITT TRIGGER BUFFER TYPICAL VIH 4.5 4.0 3.5 VIH (V) Min. 3.0 2.5 2.0 -40°C 1.5 125°C 1.0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VDD (V) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-23: PIC18(L)F1XK22 TTL BUFFER TYPICAL VIL 2.1 1.9 1.7 1.5 VIL (V) 1.3 25°C 1.1 -40°C 0.9 125°C 85°C 0.7 Max. 0.5 0.3 0.1 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VDD (V) FIGURE 27-24: PIC18(L)F1XK22 SCHMITT BUFFER TYPICAL VIL 2.0 1.8 1.6 -40°C VIL (V) 1.4 1.2 1.0 125°C Max. 0.8 0.6 0.4 0.2 1.8 2.3 2.8 3.3 3.8 4.3 4.8 5.3 VDD (V) DS40001365F-page 368 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-25: MEMLOW TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%) 33.3 Frequency (kHz) F 32.3 25°C -40°C 31.3 85°C 30.3 125°C 29.3 28.3 2 2.5 3 3.5 4 4.5 5 5.5 VDD (V) FIGURE 27-26: MEMLOW TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%) Frequency F (kHz) 32.5 32.0 2.5V 31.5 3.0V 5.5V 31.0 30.5 30.0 29.5 29.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-27: PIC18LF1XK22 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%) 33.3 32.3 31.3 Frequency (kHz) 30.3 25°C 29.3 -40°C 85°C 28.3 125°C 27.3 26.3 25.3 2 2.4 2.8 3.2 3.6 VDD (V) FIGURE 27-28: PIC18LF1XK22 TYPICAL LF-INTOSC FREQUENCY (MAX./MIN. = 31.25 kHz ± 15%) 33.0 32 0 32.0 Frequency (kH F Hz) 31.0 2.5V 3V 3.6V 30.0 29.0 28.0 27.0 26.0 -40 -20 0 20 40 60 80 100 120 Temperature (°C) DS40001365F-page 370 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 FIGURE 27-29: MEMLOW TYPICAL VOH vs. IOH 6 5 VOH (V) 4 3 5.5V 2 4.0V 3.0V 1 2.0V 0 0 5 10 15 20 25 30 35 IOH (mA) FIGURE 27-30: MEMLOW TYPICAL VOL vs. IOL 2.5 2.0 1.5 VOL (V) 1.8V 3.0 1.0 4.0V 5.5V 0.5 0.0 0 5 10 15 20 25 30 IOL (mA) 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 28.0 PACKAGING INFORMATION 28.1 Package Marking Information 20-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 20-Lead SSOP (5.30 mm) Example PIC18F13K22 -E/P e3 0910017 Example PIC18F13K22 -I/SS e3 0910017 Legend: XX...
PIC18(L)F1XK22 Package Marking Information (Continued) Example 20-Lead SOIC (7.50 mm) PIC18F14K22 -E/SO e3 0910017 20-Lead QFN (4x4x0.9 mm) PIN 1 Example PIN 1 Legend: XX...X Y YY WW NNN e3 * Note: PIC18 F14K22 E/ML e3 910017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC® designator for Matte Tin (Sn) This package is Pb-free.
PIC18(L)F1XK22 28.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N E1 NOTE 1 1 2 3 D E A2 A L c A1 b1 b eB e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV ,1&+(6 0,1 1 120 0$; 3LWFK H 7RS WR 6HDWLQJ 3ODQH $ ± ± 0ROGHG 3DFNDJH 7KLFNQHVV $
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PIC18(L)F1XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001365F-page 376 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS40001365F-page 378 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E2 2 E b 2 1 1 K N N NOTE 1 TOP VIEW L BOTTOM VIEW A A1 A3 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 0,//,0(7(56 0,1 1 120 0$; 3LWFK H 2YHUDOO +HLJKW $ 6WDQGRII $ &RQWDFW 7KLFNQHVV $ 2YHUDOO :LGW
PIC18(L)F1XK22 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ 2009-2016 Microchip Technology Inc.
PIC18(L)F1XK22 APPENDIX A: REVISION HISTORY Revision A (February 2009) Original data sheet for PIC18(L)F1XK22 devices. Revision B (04/2009) Revised data sheet title; Revised Peripheral Features section; Revised Table 3-1, Table 3-2; Revised Example 15-1; Revised Table 21-4. Revision C (10/2009) Updated Table 1-1; Updated the “Electrical Specifications” section (Figures 25-1 to 25-4; subsections 25.1, 25.2, 25.3, 25.4, 25.5, 25.6, 25.7, 25.8, Added Param No. OS09 to Table 25-2; Added Param No.
PIC18(L)F1XK22 APPENDIX B: DEVICE DIFFERENCES The differences between the devices listed in this data sheet are shown in Table . TABLE B-1: DEVICE DIFFERENCES Features PIC18F13K22 PIC18F14K22 PIC18LF13K22 PIC18LF14K22 Program Memory (Bytes) 8192 16384 8192 16384 Program Memory (Instructions) 4096 8192 4096 8192 Data Memory SRAM (bytes) 256 512 256 512 Data Memory EEPROM (bytes) 256 256 256 256 2.3 2.3 1.8 1.8 5.5 5.5 3.6 3.
PIC18(L)F1XK22 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This website is used as a means to make files and information easily available to customers.
PIC18(L)F1XK22 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
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