PIC16F87XA Data Sheet 28/40/44-Pin Enhanced Flash Microcontrollers 2003 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F87XA 28/40/44-Pin Enhanced Flash Microcontrollers Devices Included in this Data Sheet: • PIC16F873A • PIC16F874A Analog Features: • 10-bit, up to 8-channel Analog-to-Digital Converter (A/D) • Brown-out Reset (BOR) • Analog Comparator module with: - Two analog comparators - Programmable on-chip voltage reference (VREF) module - Programmable input multiplexing from device inputs and internal voltage reference - Comparator outputs are externally accessible • PIC16F876A • PIC16F877A High-Performance RI
PIC16F87XA Pin Diagrams 28-Pin PDIP, SOIC, SSOP RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RA1/AN1 RA0/AN0 MCLR/VPP RB7/PGD RB6/PGC RB5 RB4 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PIC16F873A/876A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT VSS OSC1/CLKI OSC2/CLKO RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 RC2/CCP1 RC3/SCK/SCL 28 27 26 25 24 23 22 28-Pin QFN 1 2 3 4 5 6 7 PIC16
PIC16F87XA Pin Diagrams (Continued) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6/TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2/PSP2 RA3/AN3/VREF+ RA2/AN2/VREF-/CVREF RA1/AN1 RA0/AN0 MCLR/VPP NC RB7/PGD RB6/PGC RB5 RB4 NC MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RE0/RD/AN5 RE1/WR/AN6 RE2/CS/
PIC16F87XA Table of Contents 1.0 Device Overview ......................................................................................................................................................................... 5 2.0 Memory Organization................................................................................................................................................................ 15 3.0 Data EEPROM and Flash Program Memory ...............................................................
PIC16F87XA 1.0 DEVICE OVERVIEW This document contains device specific information about the following devices: • • • • PIC16F873A PIC16F874A PIC16F876A PIC16F877A PIC16F873A/876A devices are available only in 28-pin packages, while PIC16F874A/877A devices are available in 40-pin and 44-pin packages. All devices in the PIC16F87XA family share common architecture with the following differences: The available features are summarized in Table 1-1.
PIC16F87XA FIGURE 1-1: PIC16F873A/876A BLOCK DIAGRAM 13 Flash Program Memory Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RAM File Registers 8 Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr(1) 9 Addr MUX Instruction reg Direct Addr 7 Indirect Addr 8 PORTB RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD FSR reg Status reg 8 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscillator Sta
PIC16F87XA FIGURE 1-2: PIC16F874A/877A BLOCK DIAGRAM 13 Flash Program Memory Program Bus PORTA RA0/AN0 RA1/AN1 RA2/AN2/VREF-/CVREF RA3/AN3/VREF+ RA4/T0CKI/C1OUT RA5/AN4/SS/C2OUT RAM File Registers 8 Level Stack (13-bit) 14 8 Data Bus Program Counter RAM Addr(1) PORTB 9 RB0/INT RB1 RB2 RB3/PGM RB4 RB5 RB6/PGC RB7/PGD Addr MUX Instruction reg Direct Addr 7 Indirect Addr 8 FSR reg Status reg 8 PORTC 3 Power-up Timer Instruction Decode & Control Timing Generation OSC1/CLKI OSC2/CLKO Oscilla
PIC16F87XA TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION Pin Name OSC1/CLKI OSC1 PDIP, SOIC, SSOP Pin# QFN Pin# 9 6 I/O/P Type I CLKI I OSC2/CLKO OSC2 10 7 Buffer Type ST/CMOS(3) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins). — Oscillator crystal or clock output.
PIC16F87XA TABLE 1-2: PIC16F873A/876A PINOUT DESCRIPTION (CONTINUED) Pin Name PDIP, SOIC, SSOP Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/INT RB0 INT 21 RB1 22 TTL/ST(1) 18 I/O I 19 I/O I/O RB2 23 20 RB3/PGM RB3 PGM 24 21 Digital I/O. External interrupt. TTL Digital I/O. TTL Digital I/O. TTL I/O I Digital I/O.
PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION Pin Name OSC1/CLKI OSC1 PDIP Pin# 13 PLCC TQFP Pin# Pin# 14 30 QFN Pin# I/O/P Type 32 I CLKI I OSC2/CLKO OSC2 14 15 31 33 Buffer Type ST/CMOS(4) Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. External clock source input. Always associated with pin function OSC1 (see OSC1/CLKI, OSC2/CLKO pins).
PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB1 34 37 9 10 I/O TTL Digital I/O. RB2 35 38 10 11 I/O TTL Digital I/O. RB3/PGM RB3 PGM 36 39 11 12 RB4 37 41 14 14 I/O TTL Digital I/O. RB5 38 42 15 15 I/O TTL Digital I/O.
PIC16F87XA TABLE 1-3: PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) Pin Name PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI RC0 T1OSO T1CKI 15 RC1/T1OSI/CCP2 RC1 T1OSI CCP2 16 RC2/CCP1 RC2 CCP1 17 RC3/SCK/SCL RC3 SCK 18 16 32 34 I/O O I 18 35 35 ST 19 36 36 Digital I/O. Timer1 oscillator input. Capture2 input, Compare2 output, PWM2 output. ST I/O I/O 20 37 37 Digital I/O.
PIC16F87XA TABLE 1-3: Pin Name PIC16F874A/877A PINOUT DESCRIPTION (CONTINUED) PDIP Pin# PLCC TQFP Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTD is a bidirectional I/O port or Parallel Slave Port when interfacing to a microprocessor bus. RD0/PSP0 RD0 PSP0 19 RD1/PSP1 RD1 PSP1 20 RD2/PSP2 RD2 PSP2 21 RD3/PSP3 RD3 PSP3 22 RD4/PSP4 RD4 PSP4 27 RD5/PSP5 RD5 PSP5 28 RD6/PSP6 RD6 PSP6 29 RD7/PSP7 RD7 PSP7 30 21 38 ST/TTL(3) 38 Digital I/O. Parallel Slave Port data.
PIC16F87XA NOTES: DS39582B-page 14 2003 Microchip Technology Inc.
PIC16F87XA 2.0 MEMORY ORGANIZATION There are three memory blocks in each of the PIC16F87XA devices. The program memory and data memory have separate buses so that concurrent access can occur and is detailed in this section. The EEPROM data memory block is detailed in Section 3.0 “Data EEPROM and Flash Program Memory”. Additional information on device memory may be found in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023). FIGURE 2-1: PIC16F876A/877A PROGRAM MEMORY MAP AND STACK 2.
PIC16F87XA 2.2 Data Memory Organization The data memory is partitioned into multiple banks which contain the General Purpose Registers and the Special Function Registers. Bits RP1 (Status<6>) and RP0 (Status<5>) are the bank select bits. RP1:RP0 Bank 00 0 01 1 10 2 11 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM.
PIC16F87XA FIGURE 2-3: PIC16F876A/877A REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register File Address Indirect addr.
PIC16F87XA FIGURE 2-4: PIC16F873A/874A REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PORTC PORTD(1) PORTE(1) PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON RCSTA TXREG RCREG CCPR2L CCPR2H CCP2CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F87XA 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. A list of these registers is given in Table 2-1. TABLE 2-1: Address Name The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section.
PIC16F87XA TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Details POR, BOR on page: Bank 1 80h(3) INDF 81h OPTION_REG 82h(3) PCL 83h(3) STATUS 84h(3) FSR Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Program Counter (PC) Least Significant Byte IRP RP1 RP0 TO 0000 0000 30, 150 PD Z DC C I
PIC16F87XA TABLE 2-1: Address SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: Details POR, BOR on page: Bank 2 100h(3) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 31, 150 101h TMR0 Timer0 Module Register xxxx xxxx 55, 150 102h(3) PCL Program Counter’s (PC) Least Significant Byte 0000 0000 30, 150 103h(3) STATUS 104h(3) FSR 105h — 106h IRP RP1 RP0 TO
PIC16F87XA 2.2.2.1 Status Register The Status register contains the arithmetic status of the ALU, the Reset status and the bank select bits for data memory. The Status register can be the destination for any instruction, as with any other register. If the Status register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F87XA 2.2.2.2 OPTION_REG Register Note: The OPTION_REG Register is a readable and writable register, which contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the external INT interrupt, TMR0 and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F87XA 2.2.2.3 INTCON Register Note: The INTCON register is a readable and writable register, which contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. REGISTER 2-3: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87XA 2.2.2.4 PIE1 Register Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt. The PIE1 register contains the individual enable bits for the peripheral interrupts.
PIC16F87XA 2.2.2.5 PIR1 Register Note: The PIR1 register contains the individual flag bits for the peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt bits are clear prior to enabling an interrupt.
PIC16F87XA 2.2.2.6 PIE2 Register Note: The PIE2 register contains the individual enable bits for the CCP2 peripheral interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt. REGISTER 2-6: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F87XA 2.2.2.7 PIR2 Register Note: The PIR2 register contains the flag bits for the CCP2 interrupt, the SSP bus collision interrupt, EEPROM write operation interrupt and the comparator interrupt. REGISTER 2-7: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F87XA 2.2.2.8 PCON Register Note: The Power Control (PCON) register contains flag bits to allow differentiation between a Power-on Reset (POR), a Brown-out Reset (BOR), a Watchdog Reset (WDT) and an external MCLR Reset. REGISTER 2-8: BOR is unknown on Power-on Reset. It must be set by the user and checked on subsequent Resets to see if BOR is clear, indicating a brown-out has occurred.
PIC16F87XA 2.3 PCL and PCLATH The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL register which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any Reset, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F87XA 2.5 Indirect Addressing, INDF and FSR Registers A simple program to clear RAM locations 20h-2Fh using indirect addressing is shown in Example 2-2. The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. EXAMPLE 2-2: Indirect addressing is possible by using the INDF register. Any instruction using the INDF register actually accesses the register pointed to by the File Select Register, FSR.
PIC16F87XA NOTES: DS39582B-page 32 2003 Microchip Technology Inc.
PIC16F87XA 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY The data EEPROM and Flash program memory is readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers.
PIC16F87XA REGISTER 3-1: EECON1 REGISTER (ADDRESS 18Ch) R/W-x U-0 U-0 U-0 R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — — WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
PIC16F87XA 3.3 Reading Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). The data is available in the very next cycle in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read or until it is written to by the user (during a write operation).
PIC16F87XA 3.5 Reading Flash Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>) and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory Flash controller will use the next two instruction cycles to read the data.
PIC16F87XA 3.6 Writing to Flash Program Memory Flash program memory may only be written to if the destination address is in a segment of memory that is not write-protected, as defined in bits WRT1:WRT0 of the device configuration word (Register 14-1). Flash program memory must be written in four-word blocks. A block consists of four words with sequential addresses, with a lower boundary defined by an address, where EEADR<1:0> = 00.
PIC16F87XA An example of the complete four-word write sequence is shown in Example 3-4. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing. EXAMPLE 3-4: ; ; ; ; ; ; WRITING TO FLASH PROGRAM MEMORY This write routine assumes the following: 1. A valid starting address (the least significant bits = ‘00’)is loaded in ADDRH:ADDRL 2. The 8 bytes of data are loaded, starting at the address in DATADDR 3.
PIC16F87XA 3.7 Protection Against Spurious Write 3.8 There are conditions when the device should not write to the data EEPROM or Flash program memory. To protect against spurious writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. When the data EEPROM is code-protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled.
PIC16F87XA NOTES: DS39582B-page 40 2003 Microchip Technology Inc.
PIC16F87XA 4.0 I/O PORTS Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Additional information on I/O ports may be found in the PICmicro™ Mid-Range Reference Manual (DS33023). 4.1 PORTA and the TRISA Register PORTA is a 6-bit wide, bidirectional port. The corresponding data direction register is TRISA.
PIC16F87XA FIGURE 4-2: BLOCK DIAGRAM OF RA4/T0CKI PIN CMCON<2:0> = x01 or 011 C1OUT Data Latch D Q Data Bus WR PORTA CK 1 Q TRIS Latch D Q WR TRISA CK I/O pin(1) N 0 VSS Schmitt Trigger Input Buffer Q RD TRISA Q D ENEN RD PORTA TMR0 Clock Input Note 1: I/O pin has protection diodes to VSS only.
PIC16F87XA TABLE 4-1: PORTA FUNCTIONS Name RA0/AN0 Bit# Buffer bit 0 TTL Function Input/output or analog input. RA1/AN1 bit 1 TTL Input/output or analog input. RA2/AN2/VREF-/CVREF bit 2 TTL Input/output or analog input or VREF- or CVREF. RA3/AN3/VREF+ bit 3 TTL Input/output or analog input or VREF+. RA4/T0CKI/C1OUT bit 4 ST Input/output or external clock input for Timer0 or comparator output. Output is open-drain type.
PIC16F87XA 4.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin).
PIC16F87XA TABLE 4-3: Name PORTB FUNCTIONS Bit# Buffer Function RB0/INT bit 0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit 1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit 2 TTL Input/output pin. Internal software programmable weak pull-up. RB3/PGM bit 3 TTL Input/output pin or programming pin in LVP mode. Internal software programmable weak pull-up.
PIC16F87XA 4.3 PORTC and the TRISC Register PORTC is an 8-bit wide, bidirectional port. The corresponding data direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). PORTC is multiplexed with several peripheral functions (Table 4-5).
PIC16F87XA TABLE 4-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit 0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input. RC1/T1OSI/CCP2 bit 1 ST Input/output port pin or Timer1 oscillator input or Capture2 input/ Compare2 output/PWM2 output. RC2/CCP1 bit 2 ST Input/output port pin or Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL bit 3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes.
PIC16F87XA 4.4 FIGURE 4-8: PORTD and TRISD Registers Note: PORTD and TRISD are not implemented on the 28-pin devices. Data Bus PORTD is an 8-bit port with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. WR Port PORTD can be configured as an 8-bit wide microprocessor port (Parallel Slave Port) by setting control bit, PSPMODE (TRISE<4>). In this mode, the input buffers are TTL.
PIC16F87XA 4.5 PORTE and TRISE Register Note: PORTE and TRISE are not implemented on the 28-pin devices. PORTE has three pins (RE0/RD/AN5, RE1/WR/AN6 and RE2/CS/AN7) which are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. The PORTE pins become the I/O control inputs for the microprocessor port when bit PSPMODE (TRISE<4>) is set. In this mode, the user must make certain that the TRISE<2:0> bits are set and that the pins are configured as digital inputs.
PIC16F87XA TABLE 4-10: Address SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 09h PORTE — — — — — 89h TRISE IBF OBF IBOV PSPMODE — 9Fh ADCON1 ADFM ADCS2 — — PCFG3 Legend: Value on all other Resets Bit 2 Bit 1 Bit 0 Value on: POR, BOR RE2 RE1 RE0 ---- -xxx ---- -uuu PORTE Data Direction bits PCFG2 PCFG1 PCFG0 0000 -111 0000 -111 00-- 0000 00-- 0000 x = unknown, u = unchanged, - = unimplemented, read as ‘0’.
PIC16F87XA 4.6 Parallel Slave Port The Parallel Slave Port (PSP) is not implemented on the PIC16F873A or PIC16F876A. PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (TRISE<4>) is set. In Slave mode, it is asynchronously readable and writable by the external world through RD control input pin, RE0/RD/AN5, and WR control input pin, RE1/WR/AN6. The PSP can directly interface to an 8-bit microprocessor data bus.
PIC16F87XA FIGURE 4-11: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF FIGURE 4-12: PARALLEL SLAVE PORT READ WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 CS WR RD PORTD<7:0> IBF OBF PSPIF TABLE 4-11: Address REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on all other Resets 08h PORTD 09h PORTE — — — — — 89h TRISE IBF OBF IBOV PSPMODE —
PIC16F87XA 5.0 TIMER0 MODULE Counter mode is selected by setting bit T0CS (OPTION_REG<5>). In Counter mode, Timer0 will increment either on every rising or falling edge of pin RA4/T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (OPTION_REG<4>). Clearing bit T0SE selects the rising edge. Restrictions on the external clock input are discussed in detail in Section 5.2 “Using Timer0 with an External Clock”.
PIC16F87XA 5.2 Using Timer0 with an External Clock Timer0 module means that there is no prescaler for the Watchdog Timer and vice versa. This prescaler is not readable or writable (see Figure 5-1). When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI with the internal phase clocks is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks.
PIC16F87XA TABLE 5-1: Address REGISTERS ASSOCIATED WITH TIMER0 Name 01h,101h TMR0 0Bh,8Bh, 10Bh,18Bh INTCON 81h,181h Legend: OPTION_REG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Timer0 Module Register Value on all other Resets xxxx xxxx uuuu uuuu GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 x = unknown, u = unchanged, - = unimplemented locations read as ‘0’.
PIC16F87XA NOTES: DS39582B-page 56 2003 Microchip Technology Inc.
PIC16F87XA 6.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L) which are readable and writable. The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit, TMR1IE (PIE1<0>).
PIC16F87XA 6.1 Timer1 Operation in Timer Mode Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit, T1SYNC (T1CON<2>), has no effect since the internal clock is always in sync. FIGURE 6-1: 6.2 Timer1 Counter Operation Timer1 may operate in either a Synchronous, or an Asynchronous mode, depending on the setting of the TMR1CS bit.
PIC16F87XA 6.4 Timer1 Operation in Asynchronous Counter Mode If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during Sleep and can generate an interrupt-on-overflow which will wake-up the processor. However, special precautions in software are needed to read/write the timer.
PIC16F87XA 6.7 Resetting of Timer1 Register Pair (TMR1H, TMR1L) TMR1H and TMR1L registers are not reset to 00h on a POR, or any other Reset, except by the CCP1 and CCP2 special event triggers. 6.8 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers. T1CON register is reset to 00h on a Power-on Reset, or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other Resets, the register is unaffected.
PIC16F87XA 7.0 TIMER2 MODULE Register 7-1 shows the Timer2 Control register. Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time base for the PWM mode of the CCP module(s). The TMR2 register is readable and writable and is cleared on any device Reset. Additional information on timer modules is available in the PICmicro® Mid-Range MCU Family Reference Manual (DS33023).
PIC16F87XA 7.1 Timer2 Prescaler and Postscaler The prescaler and postscaler counters are cleared when any of the following occurs: • a write to the TMR2 register • a write to the T2CON register • any device Reset (POR, MCLR Reset, WDT Reset or BOR) 7.2 Output of TMR2 The output of TMR2 (before the postscaler) is fed to the SSP module, which optionally uses it to generate the shift clock. TMR2 is not cleared when T2CON is written.
PIC16F87XA 8.0 CAPTURE/COMPARE/PWM MODULES Each Capture/Compare/PWM (CCP) module contains a 16-bit register which can operate as a: • 16-bit Capture register • 16-bit Compare register • PWM Master/Slave Duty Cycle register Both the CCP1 and CCP2 modules are identical in operation, with the exception being the operation of the special event trigger. Table 8-1 and Table 8-2 show the resources and interactions of the CCP module(s).
PIC16F87XA REGISTER 8-1: CCP1CON REGISTER/CCP2CON REGISTER (ADDRESS 17h/1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 bit 7 bit 0 bit 7-6 Unimplemented: Read as ‘0’ bit 5-4 CCPxX:CCPxY: PWM Least Significant bits Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL.
PIC16F87XA 8.1 8.1.2 Capture Mode TIMER1 MODE SELECTION In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on pin RC2/CCP1. An event is defined as one of the following: Timer1 must be running in Timer mode, or Synchronized Counter mode, for the CCP module to use the capture feature. In Asynchronous Counter mode, the capture operation may not work. • • • • 8.1.
PIC16F87XA 8.2 8.2.2 Compare Mode In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the RC2/CCP1 pin is: • Driven high • Driven low • Remains unchanged FIGURE 8-2: COMPARE MODE OPERATION BLOCK DIAGRAM Special event trigger will: reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>) and set bit GO/DONE (ADCON0<2>). Set Flag bit CCP1IF (PIR1<2>) RC2/CCP1 pin CCPR1H CCPR1L S R TRISC<2> Output Enable 8.2.
PIC16F87XA 8.3 8.3.1 PWM Mode (PWM) In Pulse Width Modulation mode, the CCPx pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTC data latch, the TRISC<2> bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTC I/O data latch. Figure 8-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F87XA 8.3.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. 2. Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISC<2> bit. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. Configure the CCP1 module for PWM operation. 3. 4. 5.
PIC16F87XA TABLE 8-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2 Value on all other Resets Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR 0Bh,8Bh, INTCON 10Bh, 18Bh GIE PEIE TMR0IE INTE RBIE TMR0IF INTF RBIF 0000 000x 0000 000u Address 0Ch PIR1 PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF 0Dh PIR2 — — — — — — — CCP2IF ---- ---0 ---- ---0 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 8Dh PIE2 — — —
PIC16F87XA NOTES: DS39582B-page 70 2003 Microchip Technology Inc.
PIC16F87XA 9.0 9.1 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE FIGURE 9-1: Internal Data Bus Read Master SSP (MSSP) Module Overview The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F87XA 9.3.1 REGISTERS The MSSP module has four registers for SPI mode operation. These are: SSPSR is the shift register used for shifting data in or out. SSPBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPSR and SSPBUF together create a double-buffered receiver. When SSPSR receives a complete byte, it is transferred to SSPBUF and the SSPIF interrupt is set.
PIC16F87XA REGISTER 9-2: SSPCON1: MSSP CONTROL REGISTER 1 (SPI MODE) (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit (Transmit mode only) 1 = The SSPBUF register is written while it is still transmitting the previous word. (Must be cleared in software.
PIC16F87XA 9.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPCON<5:0> and SSPSTAT<7:6>).
PIC16F87XA 9.3.3 ENABLING SPI I/O 9.3.4 To enable the serial port, SSP Enable bit, SSPEN (SSPCON<5>), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPCON registers and then set the SSPEN bit. This configures the SDI, SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, some must have their data direction bits (in the TRIS register) appropriately programmed.
PIC16F87XA 9.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCK. The master determines when the slave (Processor 2, Figure 9-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPBUF register is written to. If the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
PIC16F87XA 9.3.6 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCK. When the last bit is latched, the SSPIF interrupt flag bit is set. the SS pin goes high, the SDO pin is no longer driven even if in the middle of a transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable, depending on the application. While in Slave mode, the external clock is supplied by the external clock source on the SCK pin.
PIC16F87XA FIGURE 9-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS Optional SCK (CKP = 0 CKE = 0) SCK (CKP = 1 CKE = 0) Write to SSPBUF SDO bit 7 SDI (SMP = 0) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 0 bit 7 Input Sample (SMP = 0) SSPIF Interrupt Flag Next Q4 Cycle after Q2↓ SSPSR to SSPBUF FIGURE 9-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS Not Optional SCK (CKP = 0 CKE = 1) SCK (CKP = 1 CKE = 1) Write to SSPBUF SDO SDI (SMP = 0) bit 6 bit 7 bit 7 bit 5 bit 4 bit 3
PIC16F87XA 9.3.8 SLEEP OPERATION 9.3.10 In Master mode, all module clocks are halted and the transmission/reception will remain in that state until the device wakes from Sleep. After the device returns to normal mode, the module will continue to transmit/ receive data. Table 9-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 9-1: In Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device.
PIC16F87XA 9.4 I2C Mode 9.4.1 The MSSP module in I 2C mode fully implements all master and slave functions (including general call support) and provides interrupts on Start and Stop bits in hardware to determine a free bus (multi-master function). The MSSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing.
PIC16F87XA REGISTER 9-3: SSPSTAT: MSSP STATUS REGISTER (I2C MODE) (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: Slew Rate Control bit In Master or Slave mode: 1 = Slew rate control disabled for standard speed mode (100 kHz and 1 MHz) 0 = Slew rate control enabled for high-speed mode (400 kHz) bit 6 CKE: SMBus Select bit In Master or Slave mode: 1 = Enable SMBus specific inputs 0 = Disable SMBus specific inputs bit 5 D/A: Data/Addre
PIC16F87XA REGISTER 9-4: SSPCON1: MSSP CONTROL REGISTER 1 (I2C MODE) (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit In Master Transmit mode: 1 = A write to the SSPBUF register was attempted while the I2C conditions were not valid for a transmission to be started. (Must be cleared in software.
PIC16F87XA REGISTER 9-5: SSPCON2: MSSP CONTROL REGISTER 2 (I2C MODE) (ADDRESS 91h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 GCEN ACKSTAT ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 bit 7 GCEN: General Call Enable bit (Slave mode only) 1 = Enable interrupt when a general call address (0000h) is received in the SSPSR 0 = General call address disabled bit 6 ACKSTAT: Acknowledge Status bit (Master Transmit mode only) 1 = Acknowledge was not received from slave 0 = Acknowledge was rece
PIC16F87XA 9.4.2 OPERATION The MSSP module functions are enabled by setting MSSP Enable bit, SSPEN (SSPCON<5>). The SSPCON register allows control of the I 2C operation.
PIC16F87XA 9.4.3.2 Reception When the R/W bit of the address byte is clear and an address match occurs, the R/W bit of the SSPSTAT register is cleared. The received address is loaded into the SSPBUF register and the SDA line is held low (ACK). When the address byte overflow condition exists, then the No Acknowledge (ACK) pulse is given. An overflow condition is defined as either bit BF (SSPSTAT<0>) is set or bit SSPOV (SSPCON<6>) is set. An MSSP interrupt is generated for each data transfer byte.
DS39582B-page 86 CKP 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 (CKP does not reset to ‘0’ when SEN = 0) SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 7 A1 8 9 ACK R/W = 0 1 D7 3 4 D4 5 D3 Receiving Data D5 Cleared in software SSPBUF is read 2 D6 6 D2 7 D1 8 D0 9 ACK 1 D7 2 D6 3 4 D4 5 D3 Receiving Data D5 6 D2 7 D1 8 D0 Bus master terminates transfer P SSPOV is set because SSPBUF is still full. ACK is not sent.
2003 Microchip Technology Inc.
DS39582B-page 88 2 1 4 1 5 0 7 UA is set indicating that the SSPADD needs to be updated SSPBUF is written with contents of SSPSR 6 A9 A8 8 9 (CKP does not reset to ‘0’ when SEN = 0) UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 9 A0 ACK UA is set indicating that SSPADD needs to be updated Cleared by hardware when SSPADD is updated with low byte of address 7 A2 A1 Cleared in sof
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PIC16F87XA 9.4.4 CLOCK STRETCHING Both 7 and 10-bit Slave modes implement automatic clock stretching during a transmit sequence. The SEN bit (SSPCON2<0>) allows clock stretching to be enabled during receives. Setting SEN will cause the SCL pin to be held low at the end of each data receive sequence. 9.4.4.
PIC16F87XA 9.4.4.5 Clock Synchronization and the CKP Bit When the CKP bit is cleared, the SCL output is forced to ‘0’; however, setting the CKP bit will not assert the SCL output low until the SCL output is already sampled low. Therefore, the CKP bit will not assert the SCL line until an external I2C master device has already asserted the SCL line. The SCL output will remain low until the CKP bit is set and all other devices on the I2C bus have deasserted SCL.
DS39582B-page 92 CKP SSPOV (SSPCON<6>) BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S A7 2 A6 3 4 A4 5 A3 Receiving Address A5 6 A2 7 A1 8 9 ACK R/W = 0 3 4 D4 5 D3 Receiving Data D5 Cleared in software 2 D6 If BF is cleared prior to the falling edge of the 9th clock, CKP will not be reset to ‘0’ and no clock stretching will occur SSPBUF is read 1 D7 6 D2 7 D1 9 ACK 1 D7 BF is set after falling edge of the 9th clock, CKP is reset to ‘0’ and clock stretching occurs 8
2003 Microchip Technology Inc. 2 1 UA (SSPSTAT<1>) SSPOV (SSPCON<6>) CKP 3 1 4 1 5 0 6 7 A9 A8 UA is set indicating that SSPADD needs to be updated SSPBUF is written with contents of SSPSR Cleared in software BF (SSPSTAT<0>) (PIR1<3>) SSPIF 1 SCL S 1 8 9 ACK R/W = 0 A7 2 4 A4 5 A3 6 8 A0 9 ACK Note: An update of the SSPADD register before the falling edge of the ninth clock will have no effect on UA and UA will remain set.
PIC16F87XA 9.4.5 GENERAL CALL ADDRESS SUPPORT If the general call address matches, the SSPSR is transferred to the SSPBUF, the BF flag bit is set (eighth bit) and on the falling edge of the ninth bit (ACK bit), the SSPIF interrupt flag bit is set. The addressing procedure for the I2C bus is such that the first byte after the Start condition usually determines which device will be the slave addressed by the master. The exception is the general call address which can address all devices.
PIC16F87XA MASTER MODE Note: Master mode is enabled by setting and clearing the appropriate SSPM bits in SSPCON and by setting the SSPEN bit. In Master mode, the SCL and SDA lines are manipulated by the MSSP hardware. Master mode of operation is supported by interrupt generation on the detection of the Start and Stop conditions. The Stop (P) and Start (S) bits are cleared from a Reset or when the MSSP module is disabled.
PIC16F87XA 9.4.6.1 I2C Master Mode Operation The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended with a Stop condition or with a Repeated Start condition. Since the Repeated Start condition is also the beginning of the next serial transfer, the I2C bus will not be released. In Master Transmitter mode, serial data is output through SDA while SCL outputs the serial clock.
PIC16F87XA 9.4.7 BAUD RATE GENERATOR In I2C Master mode, the Baud Rate Generator (BRG) reload value is placed in the lower 7 bits of the SSPADD register (Figure 9-17). When a write occurs to SSPBUF, the Baud Rate Generator will automatically begin counting. The BRG counts down to 0 and stops until another reload has taken place. The BRG count is decremented twice per instruction cycle (TCY) on the Q2 and Q4 clocks. In I2C Master mode, the BRG is reloaded automatically.
PIC16F87XA 9.4.7.1 Clock Arbitration Clock arbitration occurs when the master, during any receive, transmit or Repeated Start/Stop condition, deasserts the SCL pin (SCL allowed to float high). When the SCL pin is allowed to float high, the Baud Rate Generator (BRG) is suspended from counting until the SCL pin is actually sampled high. When the FIGURE 9-18: SCL pin is sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and begins counting.
PIC16F87XA 9.4.8 I2C MASTER MODE START CONDITION TIMING 9.4.8.1 If the user writes the SSPBUF when a Start sequence is in progress, the WCOL is set and the contents of the buffer are unchanged (the write doesn’t occur). To initiate a Start condition, the user sets the Start condition enable bit, SEN (SSPCON2<0>). If the SDA and SCL pins are sampled high, the Baud Rate Generator is reloaded with the contents of SSPADD<6:0> and starts its count.
PIC16F87XA 9.4.9 I2C MASTER MODE REPEATED START CONDITION TIMING Immediately following the SSPIF bit getting set, the user may write the SSPBUF with the 7-bit address in 7-bit mode or the default first address in 10-bit mode. After the first eight bits are transmitted and an ACK is received, the user may then transmit an additional eight bits of address (10-bit mode) or eight bits of data (7-bit mode).
PIC16F87XA 9.4.10 I2C MASTER MODE TRANSMISSION Transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the SSPBUF register. This action will set the Buffer Full flag bit, BF, and allow the Baud Rate Generator to begin counting and start the next transmission. Each bit of address/data will be shifted out onto the SDA pin after the falling edge of SCL is asserted (see data hold time specification, parameter #106).
DS39582B-page 102 S R/W PEN SEN BF (SSPSTAT<0>) SSPIF SCL SDA A6 A5 A4 A3 A2 A1 3 4 5 Cleared in software 2 6 7 8 After Start condition, SEN cleared by hardware SSPBUF written 1 9 D7 1 SCL held low while CPU responds to SSPIF ACK = 0 R/W = 0 SSPBUF written with 7-bit address and R/W. Start transmit.
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PIC16F87XA 9.4.12 ACKNOWLEDGE SEQUENCE TIMING 9.4.13 A Stop bit is asserted on the SDA pin at the end of a receive/transmit by setting the Stop Sequence Enable bit, PEN (SSPCON2<2>). At the end of a receive/ transmit, the SCL line is held low after the falling edge of the ninth clock. When the PEN bit is set, the master will assert the SDA line low. When the SDA line is sampled low, the Baud Rate Generator is reloaded and counts down to 0.
PIC16F87XA 9.4.14 SLEEP OPERATION 9.4.17 2 While in Sleep mode, the I C module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from Sleep (if the MSSP interrupt is enabled). 9.4.15 EFFECT OF A RESET A Reset disables the MSSP module and terminates the current transfer. 9.4.16 MULTI-MASTER MODE In Multi-Master mode, the interrupt generation on the detection of the Start and Stop conditions allows the determination of when the bus is free.
PIC16F87XA 9.4.17.1 Bus Collision During a Start Condition During a Start condition, a bus collision occurs if: a) b) SDA or SCL are sampled low at the beginning of the Start condition (Figure 9-26). SCL is sampled low before SDA is asserted low (Figure 9-27). During a Start condition, both the SDA and the SCL pins are monitored. If the SDA pin is sampled low during this count, the BRG is reset and the SDA line is asserted early (Figure 9-28).
PIC16F87XA FIGURE 9-27: BUS COLLISION DURING START CONDITION (SCL = 0) SDA = 0, SCL = 1 TBRG TBRG SDA SCL Set SEN, enable Start sequence if SDA = 1, SCL = 1 SCL = 0 before SDA = 0, bus collision occurs. Set BCLIF. SEN SCL = 0 before BRG time-out, bus collision occurs. Set BCLIF.
PIC16F87XA 9.4.17.2 Bus Collision During a Repeated Start Condition During a Repeated Start condition, a bus collision occurs if: a) b) If SCL goes from high to low before the BRG times out and SDA has not already been asserted, a bus collision occurs. In this case, another master is attempting to transmit a data ‘1’ during the Repeated Start condition (Figure 9-30). A low level is sampled on SDA when SCL goes from low level to high level.
PIC16F87XA 9.4.17.3 Bus Collision During a Stop Condition The Stop condition begins with SDA asserted low. When SDA is sampled low, the SCL pin is allowed to float. When the pin is sampled high (clock arbitration), the Baud Rate Generator is loaded with SSPADD<6:0> and counts down to 0. After the BRG times out, SDA is sampled. If SDA is sampled low, a bus collision has occurred. This is due to another master attempting to drive a data ‘0’ (Figure 9-31).
PIC16F87XA NOTES: DS39582B-page 110 2003 Microchip Technology Inc.
PIC16F87XA 10.0 ADDRESSABLE UNIVERSAL SYNCHRONOUS ASYNCHRONOUS RECEIVER TRANSMITTER (USART) The USART can be configured in the following modes: • Asynchronous (full-duplex) • Synchronous – Master (half-duplex) • Synchronous – Slave (half-duplex) The Universal Synchronous Asynchronous Receiver Transmitter (USART) module is one of the two serial I/O modules. (USART is also known as a Serial Communications Interface or SCI.
PIC16F87XA REGISTER 10-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-x SPEN RX9 SREN CREN ADDEN FERR OERR RX9D bit 7 bit 0 bit 7 SPEN: Serial Port Enable bit 1 = Serial port enabled (configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6 RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5 SREN: Single Receive Enable bit Asynchronous mode: Don’t care.
PIC16F87XA 10.1 USART Baud Rate Generator (BRG) It may be advantageous to use the high baud rate (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16 (X + 1)) equation can reduce the baud rate error in some cases. The BRG supports both the Asynchronous and Synchronous modes of the USART. It is a dedicated 8-bit baud rate generator. The SPBRG register controls the period of a free running 8-bit timer. In Asynchronous mode, bit BRGH (TXSTA<2>) also controls the baud rate.
PIC16F87XA TABLE 10-3: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0) FOSC = 20 MHz BAUD RATE (K) % ERROR KBAUD FOSC = 16 MHz SPBRG value (decimal) % ERROR KBAUD FOSC = 10 MHz SPBRG value (decimal) KBAUD % ERROR SPBRG value (decimal) 0.3 - - - - - - - - - 1.2 1.221 1.75 255 1.202 0.17 207 1.202 0.17 129 2.4 2.404 0.17 129 2.404 0.17 103 2.404 0.17 64 9.6 9.766 1.73 31 9.615 0.16 25 9.766 1.73 15 19.2 19.531 1.72 15 19.231 0.16 12 19.531 1.72 7 28.
PIC16F87XA 10.2 USART Asynchronous Mode enabled/disabled by setting/clearing enable bit, TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the state of enable bit TXIE and cannot be cleared in software. It will reset only when new data is loaded into the TXREG register. While flag bit TXIF indicates the status of the TXREG register, another bit, TRMT (TXSTA<1>), shows the status of the TSR register. Status bit TRMT is a read-only bit which is set when the TSR register is empty.
PIC16F87XA When setting up an Asynchronous Transmission, follow these steps: 5. 1. 6. Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH (Section 10.1 “USART Baud Rate Generator (BRG)”). Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. If interrupts are desired, then set enable bit TXIE. If 9-bit transmission is desired, then set transmit bit TX9. 2. 3. 4.
PIC16F87XA 10.2.2 USART ASYNCHRONOUS RECEIVER The receiver block diagram is shown in Figure 10-4. The data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually a high-speed shifter, operating at x16 times the baud rate; whereas the main receive serial shifter operates at the bit rate or at FOSC. Once Asynchronous mode is selected, reception is enabled by setting bit CREN (RCSTA<4>). The heart of the receiver is the Receive (Serial) Shift Register (RSR).
PIC16F87XA FIGURE 10-5: ASYNCHRONOUS RECEPTION Start bit bit 0 RX (pin) bit 1 bit 7/8 Stop bit Rcv Shift Reg Rcv Buffer Reg Start bit bit 7/8 bit 0 Start bit bit 7/8 Stop bit Word 2 RCREG Word 1 RCREG Read Rcv Buffer Reg RCREG Stop bit RCIF (Interrupt Flag) OERR bit CREN Note: This timing diagram shows three words appearing on the RX input. The RCREG (Receive Buffer) is read after the third word, causing the OERR (Overrun Error) bit to be set.
PIC16F87XA 10.2.3 SETTING UP 9-BIT MODE WITH ADDRESS DETECT When setting up an Asynchronous Reception with address detect enabled: • Initialize the SPBRG register for the appropriate baud rate. If a high-speed baud rate is desired, set bit BRGH. • Enable the asynchronous serial port by clearing bit SYNC and setting bit SPEN. • If interrupts are desired, then set enable bit RCIE. • Set bit RX9 to enable 9-bit reception. • Set ADDEN to enable address detect.
PIC16F87XA FIGURE 10-7: ASYNCHRONOUS RECEPTION WITH ADDRESS DETECT Start bit RC7/RX/DT (pin) bit 0 bit 1 bit 8 Stop bit Start bit bit 0 bit 8 Stop bit Load RSR Bit 8 = 0, Data Byte Word 1 RCREG Bit 8 = 1, Address Byte Read RCIF Note: This timing diagram shows a data byte followed by an address byte. The data byte is not read into the RCREG (Receive Buffer) because ADDEN = 1.
PIC16F87XA 10.3 USART Synchronous Master Mode In Synchronous Master mode, the data is transmitted in a half-duplex manner (i.e., transmission and reception do not occur at the same time). When transmitting data, the reception is inhibited and vice versa. Synchronous mode is entered by setting bit, SYNC (TXSTA<4>). In addition, enable bit, SPEN (RCSTA<7>), is set in order to configure the RC6/TX/CK and RC7/RX/DT I/O pins to CK (clock) and DT (data) lines, respectively.
PIC16F87XA TABLE 10-8: Address REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 0000 0000 0000 0000 CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 Name 0Bh, 8Bh, INTCON 10Bh,18Bh 0
PIC16F87XA 10.3.2 USART SYNCHRONOUS MASTER RECEPTION data. Reading the RCREG register will load bit RX9D with a new value, therefore, it is essential for the user to read the RCSTA register before reading RCREG in order not to lose the old RX9D information. Once Synchronous mode is selected, reception is enabled by setting either enable bit, SREN (RCSTA<5>), or enable bit, CREN (RCSTA<4>). Data is sampled on the RC7/RX/DT pin on the falling edge of the clock.
PIC16F87XA FIGURE 10-11: SYNCHRONOUS RECEPTION (MASTER MODE, SREN) Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit ‘0’ ‘0’ RCIF bit (Interrupt) Read RXREG Note: Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRG = 0. 10.
PIC16F87XA TABLE 10-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION Address Name 0Bh, 8Bh, INTCON 10Bh,18Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets GIE PEIE TMR0IE INTE RBIE TMR0IF INTF R0IF 0000 000x 0000 000u PSPIF(1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 SPEN RX9 SREN CREN ADDEN 0Ch PIR1 18h RCSTA 19h TXREG USART Transmit Register 8Ch PIE1 PSPIE(1) ADIE RCIE TXIE SSPIE
PIC16F87XA NOTES: DS39582B-page 126 2003 Microchip Technology Inc.
PIC16F87XA 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers. These registers are: The Analog-to-Digital (A/D) Converter module has five inputs for the 28-pin devices and eight for the 40/44-pin devices. The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has high and low-voltage reference input that is software selectable to some combination of VDD, VSS, RA2 or RA3.
PIC16F87XA REGISTER 11-2: ADCON1 REGISTER (ADDRESS 9Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified. Six (6) Most Significant bits of ADRESH are read as ‘0’. 0 = Left justified. Six (6) Least Significant bits of ADRESL are read as ‘0’.
PIC16F87XA The ADRESH:ADRESL registers contain the 10-bit result of the A/D conversion. When the A/D conversion is complete, the result is loaded into this A/D Result register pair, the GO/DONE bit (ADCON0<2>) is cleared and the A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 11-1. 2. 3. 4. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16F87XA 11.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch impedance (RSS) directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD); see Figure 11-2.
PIC16F87XA 11.2 Selecting the A/D Conversion Clock 11.3 The ADCON1 and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input). If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. The A/D conversion time per bit is defined as TAD. The A/D conversion requires a minimum 12 TAD per 10-bit conversion. The source of the A/D conversion clock is software selected.
PIC16F87XA 11.4 A/D Conversions is aborted, the next acquisition on the selected channel is automatically started. The GO/DONE bit can then be set to start the conversion. Clearing the GO/DONE bit during a conversion will abort the current conversion. The A/D Result register pair will NOT be updated with the partially completed A/D conversion sample.
PIC16F87XA 11.5 A/D Operation During Sleep Note: The A/D module can operate during Sleep mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed which eliminates all digital switching noise from the conversion. When the conversion is completed, the GO/DONE bit will be cleared and the result loaded into the ADRES register.
PIC16F87XA NOTES: DS39582B-page 134 2003 Microchip Technology Inc.
PIC16F87XA 12.0 COMPARATOR MODULE The comparator module contains two analog comparators. The inputs to the comparators are multiplexed with I/O port pins RA0 through RA3, while the outputs are multiplexed to pins RA4 and RA5. The on-chip voltage reference (Section 13.0 “Comparator Voltage Reference Module”) can also be an input to the comparators. REGISTER 12-1: The CMCON register (Register 12-1) controls the comparator input and output multiplexers.
PIC16F87XA 12.1 Comparator Configuration There are eight modes of operation for the comparators. The CMCON register is used to select these modes. Figure 12-1 shows the eight possible modes. The TRISA register controls the data direction of the comparator pins for each mode.
PIC16F87XA 12.2 12.3.2 Comparator Operation INTERNAL REFERENCE SIGNAL A single comparator is shown in Figure 12-2 along with the relationship between the analog input levels and the digital output. When the analog input at VIN+ is less than the analog input VIN-, the output of the comparator is a digital low level. When the analog input at VIN+ is greater than the analog input VIN-, the output of the comparator is a digital high level.
PIC16F87XA FIGURE 12-3: COMPARATOR OUTPUT BLOCK DIAGRAM Port Pins MULTIPLEX + CxINV To RA4 or RA5 Pin Bus Data Q Read CMCON Set CMIF bit D EN Q From Other Comparator D EN CL Read CMCON Reset 12.6 Comparator Interrupts The comparator interrupt flag is set whenever there is a change in the output value of either comparator. Software will need to maintain information about the status of the output bits, as read from CMCON<7:6>, to determine the actual change that occurred.
PIC16F87XA 12.7 Comparator Operation During Sleep 12.9 When a comparator is active and the device is placed in Sleep mode, the comparator remains active and the interrupt is functional if enabled. This interrupt will wake-up the device from Sleep mode when enabled. While the comparator is powered up, higher Sleep currents than shown in the power-down current specification will occur. Each operational comparator will consume additional current as shown in the comparator specifications.
PIC16F87XA TABLE 12-1: Address REGISTERS ASSOCIATED WITH COMPARATOR MODULE Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR Value on all other Resets 9Ch CMCON C2OUT C1OUT C2INV C1INV CIS CM2 CM1 CM0 0000 0111 0000 0111 9Dh CVRCON CVREN CVROE CVRR — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 PEIE/ GIEL TMR0IE INTIE RBIE TMR0IF INTIF RBIF 0000 000x 0000 000u 0Bh, 8Bh, INTCON 10Bh,18Bh GIE/ GIEH 0Dh PIR2 — CMIF — — BCLIF LVDIF TMR3IF CCP2IF -0
PIC16F87XA 13.0 COMPARATOR VOLTAGE REFERENCE MODULE The Comparator Voltage Reference Generator is a 16-tap resistor ladder network that provides a fixed voltage reference when the comparators are in mode ‘110’. A programmable register controls the function of the reference generator. Register 13-1 lists the bit functions of the CVRCON register.
PIC16F87XA FIGURE 13-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VDD 16 Stages CVREN 8R R R R R 8R CVRR RA2/AN2/VREF-/CVREF CVROE CVREF Input to Comparator TABLE 13-1: Address CVR3 CVR2 CVR1 CVR0 16:1 Analog MUX REGISTERS ASSOCIATED WITH COMPARATOR VOLTAGE REFERENCE Name Bit 7 Bit 6 Bit 5 9Dh CVRCON CVREN CVROE CVRR 9Ch CMCON Value on all other Resets Bit 3 Bit 2 Bit 1 — CVR3 CVR2 CVR1 CVR0 000- 0000 000- 0000 CIS CM2 CM1 CM0 C2OUT C1OUT C2INV C1INV Bit 0 Value on PO
PIC16F87XA 14.0 SPECIAL FEATURES OF THE CPU All PIC16F87XA devices have a host of features intended to maximize system reliability, minimize cost through elimination of external components, provide power saving operating modes and offer code protection.
PIC16F87XA REGISTER 14-1: R/P-1 U-0 CP — CONFIGURATION WORD (ADDRESS 2007h)(1) R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 DEBUG WRT1 WRT0 CPD LVP R/P-1 U-0 U-0 BOREN — — R/P-1 R/P-1 R/P-1 R/P-1 PWRTEN WDTEN FOSC1 FOSC0 bit 13 bit0 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All program memory code-protected bit 12 Unimplemented: Read as ‘1’ bit 11 DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins
PIC16F87XA 14.2 FIGURE 14-2: Oscillator Configurations 14.2.1 OSCILLATOR TYPES The PIC16F87XA can be operated in four different oscillator modes. The user can program two configuration bits (FOSC1 and FOSC0) to select one of these four modes: • • • • LP XT HS RC In XT, LP or HS modes, a crystal or ceramic resonator is connected to the OSC1/CLKI and OSC2/CLKO pins to establish oscillation (Figure 14-1). The PIC16F87XA oscillator design requires the use of a parallel cut crystal.
PIC16F87XA TABLE 14-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Osc Type Crystal Freq. Cap. Range C1 Cap. Range C2 LP 32 kHz 33 pF 33 pF 200 kHz 15 pF 15 pF 200 kHz 47-68 pF 47-68 pF 1 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 4 MHz 15 pF 15 pF 8 MHz 15-33 pF 15-33 pF 20 MHz 15-33 pF 15-33 pF XT HS These values are for design guidance only. See notes following this table. 14.2.
PIC16F87XA 14.3 Reset The PIC16F87XA differentiates between various kinds of Reset: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during Sleep WDT Reset (during normal operation) WDT Wake-up (during Sleep) Brown-out Reset (BOR) state” on Power-on Reset (POR), on the MCLR and WDT Reset, on MCLR Reset during Sleep and Brownout Reset (BOR). They are not affected by a WDT wake-up which is viewed as the resumption of normal operation.
PIC16F87XA 14.4 MCLR 14.6 PIC16F87XA devices have a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin differs from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both Resets and current consumption outside of device specification during the Reset event.
PIC16F87XA 14.10 Power Control/Status Register (PCON) When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable and is, therefore, not valid at any time. The Power Control/Status Register, PCON, has up to two bits depending upon the device. Bit 1 is the Power-on Reset Status bit, POR. It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Bit 0 is the Brown-out Reset Status bit, BOR.
PIC16F87XA TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt W 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu INDF 73A 74A 76A 77A N/A N/A N/A TMR0 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu PCL 73A 74A 76A 77A 0000 0000 0000 0000 PC + 1(2) STATUS 73A 74A 76A 77A 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 73A 74A 76A 77A xxxx xxxx uuuu uuuu uuuu uuuu
PIC16F87XA TABLE 14-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Devices Power-on Reset, Brown-out Reset MCLR Resets, WDT Reset Wake-up via WDT or Interrupt TRISD 73A 74A 76A 77A 1111 1111 1111 1111 uuuu uuuu TRISE 73A 74A 76A 77A 0000 -111 0000 -111 uuuu -uuu 73A 74A 76A 77A r000 0000 r000 0000 ruuu uuuu 73A 74A 76A 77A 0000 0000 0000 0000 uuuu uuuu PIE1 PIE2 73A 74A 76A 77A -0-0 0--0 -0-0 0--0 -u-u u--u PCON 73A 74A 76A 77A ---- --qq
PIC16F87XA FIGURE 14-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 FIGURE 14-8: VDD MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset FIGURE 14-9: SLOW RISE TIME (MCLR TIED TO VDD VIA RC NETWORK) 5V VDD 1V 0V MCLR Internal POR TPWRT PWRT Time-out TOST OST Time-out Internal Reset DS39582B-page 152 2003 Microchip
PIC16F87XA 14.11 Interrupts The PIC16F87XA family has up to 15 sources of interrupt. The Interrupt Control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit. A global interrupt enable bit, GIE (INTCON<7>), enables (if set) all unmasked interrupts or disables (if cleared) all interrupts.
PIC16F87XA 14.11.1 INT INTERRUPT 14.12 Context Saving During Interrupts External interrupt on the RB0/INT pin is edge triggered, either rising if bit INTEDG (OPTION_REG<6>) is set or falling if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit, INTF (INTCON<1>), is set. This interrupt can be disabled by clearing enable bit, INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F87XA 14.13 Watchdog Timer (WDT) WDT time-out period values may be found in Section 17.0 “Electrical Characteristics” under parameter #31. Values for the WDT prescaler (actually a postscaler but shared with the Timer0 prescaler) may be assigned using the OPTION_REG register. The Watchdog Timer is a free running, on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKI pin.
PIC16F87XA 14.14 Power-down Mode (Sleep) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (Status<3>) is cleared, the TO (Status<4>) bit is set and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low or high-impedance).
PIC16F87XA FIGURE 14-12: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency(2) GIE bit (INTCON<7>) Processor in Sleep INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 Instruction Fetched Inst(PC) = Sleep Inst(PC + 1) Inst(PC + 2) Instruction Executed Inst(PC - 1) Sleep Inst(PC + 1) PC + 2 Dummy cycle 0004h 0005h Inst(0004h) Inst(0005h) Dummy cycle Inst(0004h) N
PIC16F87XA 14.18 In-Circuit Serial Programming PIC16F87XA microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
PIC16F87XA 15.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations • Literal and control operations Each PIC16 instruction is a 14-bit word divided into an opcode which specifies the instruction type and one or more operands which further specify the operation of the instruction.
PIC16F87XA TABLE 15-2: PIC16F87XA INSTRUCTION SET Mnemonic, Operands 14-Bit Opcode Description Cycles MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W
PIC16F87XA 15.2 Instruction Descriptions ADDLW Add Literal and W BCF Bit Clear f Syntax: [ label ] ADDLW Syntax: [ label ] BCF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 0≤b≤7 Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: 0 → (f) Description: The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: None Description: Bit ‘b’ in register ‘f’ is cleared.
PIC16F87XA CALL Call Subroutine CLRWDT Clear Watchdog Timer Syntax: [ label ] CALL k Syntax: [ label ] CLRWDT Operands: 0 ≤ k ≤ 2047 Operands: None Operation: (PC)+ 1→ TOS, k → PC<10:0>, (PCLATH<4:3>) → PC<12:11> Operation: Status Affected: None 00h → WDT 0 → WDT prescaler, 1 → TO 1 → PD Description: Call Subroutine. First, return address (PC+1) is pushed onto the stack. The eleven-bit immediate address is loaded into PC bits <10:0>. The upper bits of the PC are loaded from PCLATH.
PIC16F87XA DECFSZ Decrement f, Skip if 0 INCFSZ Increment f, Skip if 0 Syntax: [ label ] DECFSZ f,d Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f) - 1 → (destination); skip if result = 0 Operation: (f) + 1 → (destination), skip if result = 0 Status Affected: None Status Affected: None Description: The contents of register ‘f’ are decremented. If ‘d’ is ‘0’, the result is placed in the W register.
PIC16F87XA RLF Rotate Left f through Carry SLEEP Syntax: [ label ] RLF Syntax: [ label ] SLEEP Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: None Operation: Operation: See description below Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry flag. If ‘d’ is ‘0’, the result is placed in the W register. If ‘d’ is ‘1’, the result is stored back in register ‘f’.
PIC16F87XA SWAPF Swap Nibbles in f XORWF Exclusive OR W with f Syntax: [ label ] SWAPF f,d Syntax: [ label ] XORWF Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (f<3:0>) → (destination<7:4>), (f<7:4>) → (destination<3:0>) Operation: (W) .XOR. (f) → (destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register ‘f’. If ‘d’ is ‘0’, the result is stored in the W register.
PIC16F87XA NOTES: DS39582B-page 166 2003 Microchip Technology Inc.
PIC16F87XA 16.
PIC16F87XA 16.3 MPLAB C17 and MPLAB C18 C Compilers The MPLAB C17 and MPLAB C18 Code Development Systems are complete ANSI C compilers for Microchip’s PIC17CXXX and PIC18CXXX family of microcontrollers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 16.
PIC16F87XA 16.9 MPLAB ICE 2000 High Performance Universal In-Circuit Emulator The MPLAB ICE 2000 universal in-circuit emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PICmicro microcontrollers. Software control of the MPLAB ICE 2000 in-circuit emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment.
PIC16F87XA 16.14 PICDEM 1 PICmicro Demonstration Board 16.17 PICDEM 3 PIC16C92X Demonstration Board The PICDEM 1 demonstration board demonstrates the capabilities of the PIC16C5X (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and PIC17C44. All necessary hardware and software is included to run basic demo programs.
PIC16F87XA 16.20 PICDEM 18R PIC18C601/801 Demonstration Board 16.23 PICDEM USB PIC16C7X5 Demonstration Board The PICDEM 18R demonstration board serves to assist development of the PIC18C601/801 family of Microchip microcontrollers. It provides hardware implementation of both 8-bit Multiplexed/Demultiplexed and 16-bit Memory modes. The board includes 2 Mb external Flash memory and 128 Kb SRAM memory, as well as serial EEPROM, allowing access to the wide range of memory types supported by the PIC18C601/801.
PIC16F87XA NOTES: DS39582B-page 172 2003 Microchip Technology Inc.
PIC16F87XA 17.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias................................................................................................................ .-55 to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD, MCLR. and RA4) ......................................... -0.
PIC16F87XA FIGURE 17-1: PIC16F87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL, EXTENDED) 6.0V 5.5V 5.0V PIC16F87XA Voltage 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 20 MHz Frequency FIGURE 17-2: PIC16LF87XA VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 6.0V 5.5V Voltage 5.0V 4.5V 4.0V PIC16LF87XA 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (6.0 MHz/V) (VDDAPPMIN – 2.0V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F873A/874A/876A/877A (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F873A/874A/876A/877A (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87XA 17.1 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F873A/874A/876A/877A (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F87XA 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC specification (Section 17.1) DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ† Max Units Conditions VSS — 0.15 VDD V For entire VDD range VSS — 0.8V V 4.
PIC16F87XA 17.2 DC Characteristics: PIC16F873A/874A/876A/877A (Industrial, Extended) PIC16LF873A/874A/876A/877A (Industrial) (Continued) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC specification (Section 17.1) DC CHARACTERISTICS Param No. Sym VOL Characteristic Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.
PIC16F87XA TABLE 17-1: COMPARATOR SPECIFICATIONS Operating Conditions: Param No. D300 3.0V < VDD < 5.5V, -40°C < TA < +85°C (unless otherwise stated) 4.0V < VDD < 5.5V, -40°C < TA < +125°C (unless otherwise stated) Sym VIOFF Characteristics Min Typ Max Units — ± 5.0 ± 10 mV Input Offset Voltage D301 VICM Input Common Mode Voltage* 0 - VDD – 1.
PIC16F87XA 17.3 Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F87XA FIGURE 17-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 17-3: Param No. EXTERNAL CLOCK TIMING REQUIREMENTS Symbol FOSC Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC External CLKI Period (Note 1) Oscillator Period (Note 1) Min Typ† Max Units Conditions DC — 1 MHz XT and RC Osc mode DC — 20 MHz HS Osc mode DC — 32 kHz DC — 4 MHz RC Osc mode 0.
PIC16F87XA FIGURE 17-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O pin (Input) 15 17 I/O pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 17-3 for load conditions. TABLE 17-4: Param No.
PIC16F87XA FIGURE 17-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal Reset Watchdog Timer Reset 31 34 34 I/O pins Note: Refer to Figure 17-3 for load conditions. FIGURE 17-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 17-5: Param No.
PIC16F87XA FIGURE 17-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RC0/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 17-3 for load conditions. TABLE 17-6: Param No.
PIC16F87XA FIGURE 17-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2) RC1/T1OSI/CCP2 and RC2/CCP1 (Capture Mode) 50 51 52 RC1/T1OSI/CCP2 and RC2/CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 17-3 for load conditions. TABLE 17-7: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2) Param Symbol No. 50* TCCL Characteristic CCP1 and CCP2 Input Low Time No Prescaler With Prescaler 51* TCCH CCP1 and CCP2 Input High Time Min Standard(F) Extended(LF) 0.
PIC16F87XA FIGURE 17-10: PARALLEL SLAVE PORT TIMING (PIC16F874A/877A ONLY) RE2/CS RE0/RD RE1/WR 65 RD7:RD0 62 64 63 Note: Refer to Figure 17-3 for load conditions. TABLE 17-8: Param No.
PIC16F87XA FIGURE 17-11: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit 6 - - - - - -1 MSb SDO LSb 75, 76 SDI MSb In Bit 6 - - - -1 LSb In 74 73 Note: Refer to Figure 17-3 for load conditions. FIGURE 17-12: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit 6 - - - - - -1 LSb Bit 6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 17-3 for load conditions.
PIC16F87XA FIGURE 17-13: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 MSb SDO LSb Bit 6 - - - - - -1 77 75, 76 SDI MSb In LSb In Bit 6 - - - -1 74 73 Note: Refer to Figure 17-3 for load conditions. FIGURE 17-14: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 MSb SDO Bit 6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit 6 - - - -1 LSb In 74 Note: Refer to Figure 17-3 for load conditions.
PIC16F87XA TABLE 17-9: Param No.
PIC16F87XA TABLE 17-10: I2C BUS START/STOP BITS REQUIREMENTS Param No.
PIC16F87XA TABLE 17-11: I2C BUS DATA REQUIREMENTS Param No. 100 Sym THIGH Characteristic Clock High Time Min Max Units 100 kHz mode 4.0 — µs 400 kHz mode 0.6 — µs 0.5 TCY — 100 kHz mode 4.7 — µs 400 kHz mode 1.3 — µs 0.5 TCY — SSP Module 101 TLOW Clock Low Time SSP Module 102 103 TR TF SDA and SCL Rise Time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.1 CB 300 ns SDA and SCL Fall Time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.
PIC16F87XA FIGURE 17-17: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING RC6/TX/CK pin 121 121 RC7/RX/DT pin 120 122 Note: Refer to Figure 17-3 for load conditions. TABLE 17-12: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS Param No.
PIC16F87XA TABLE 17-14: A/D CONVERTER CHARACTERISTICS:PIC16F873A/874A/876A/877A (INDUSTRIAL) PIC16LF873A/874A/876A/877A (INDUSTRIAL) Param No. Sym Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10-bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral Linearity Error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential Linearity Error — — <±1 LSb VREF = VDD = 5.
PIC16F87XA FIGURE 17-19: A/D CONVERSION TIMING 1 TCY BSF ADCON0, GO (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 0 NEW_DATA OLD_DATA ADRES ADIF GO DONE Sampling Stopped SAMPLE Note: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 17-15: A/D CONVERSION REQUIREMENTS Param Symbol No. 130 TAD Characteristic A/D Clock Period — — µs TOSC based, VREF ≥ 3.
PIC16F87XA NOTES: DS39582B-page 196 2003 Microchip Technology Inc.
PIC16F87XA 18.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Note: The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
PIC16F87XA FIGURE 18-3: TYPICAL IDD vs. FOSC OVER VDD (XT MODE) 1.8 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 1.6 5.5V 1.4 5.0V 1.2 4.5V IDD (mA) 4.0V 1.0 3.5V 0.8 3.0V 2.5V 0.6 2.0V 0.4 0.2 0.0 0 500 1000 1500 2000 2500 3000 3500 4000 3500 4000 FOSC (MHz) FIGURE 18-4: MAXIMUM IDD vs. FOSC OVER VDD (XT MODE) 2.
PIC16F87XA FIGURE 18-5: TYPICAL IDD vs. FOSC OVER VDD (LP MODE) 70 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 60 5.5V 5.0V 50 4.5V IDD (uA) 40 4.0V 3.5V 30 3.0V 2.5V 20 2.0V 10 0 20 30 40 50 60 70 80 90 100 FOSC (kHz) FIGURE 18-6: MAXIMUM IDD vs. FOSC OVER VDD (LP MODE) 120 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 100 5.5V 5.0V 4.5V 80 IDD (uA) 4.
PIC16F87XA FIGURE 18-7: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 20 pF, +25°C) 4.5 Operation above 4 MHz is not recommended 4.0 5.1 kOhm 3.5 Freq (MHz) 3.0 2.5 10 kOhm 2.0 1.5 1.0 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-8: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 100 pF, +25°C) 2.5 2.0 3.3 kOhm Freq (MHz) 1.5 5.1 kOhm 1.0 10 kOhm 0.5 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.
PIC16F87XA FIGURE 18-9: AVERAGE FOSC vs. VDD FOR VARIOUS VALUES OF R (RC MODE, C = 300 pF, +25°C) 0.9 0.8 3.3 kOhm 0.7 0.6 Freq (MHz) 5.1 kOhm 0.5 0.4 10 kOhm 0.3 0.2 0.1 100 kOhm 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-10: IPD vs. VDD, -40°C TO +125°C (SLEEP MODE, ALL PERIPHERALS DISABLED) 100 Max (125°C) 10 Max (85°C) IPD (uA) 1 0.1 0.01 Typ (25°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 0.001 2.
PIC16F87XA FIGURE 18-11: TYPICAL AND MAXIMUM ∆ITMR1 vs. VDD OVER TEMPERATURE (-10°C TO +70°C, TIMER1 WITH OSCILLATOR, XTAL = 32 kHz, C1 AND C2 = 47 pF) 14 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-10°C to +70°C) Minimum: mean – 3σ (-10°C to +70°C) 12 Max Max(+70°C) (70C) 10 (µA) IPD (uA) 8 Typ Typ(+25°C) (25C) 6 4 2 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-12: TYPICAL AND MAXIMUM ∆IWDT vs.
PIC16F87XA FIGURE 18-13: ∆IBOR vs. VDD OVER TEMPERATURE 1,000 Max (125°C) Typ (25°C) Device in Sleep IDD (µA) Indeterminant State Device in Reset 100 Note: Device current in Reset depends on oscillator mode, frequency and circuit. Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) Typ (25°C) 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-14: TYPICAL, MINIMUM AND MAXIMUM WDT PERIOD vs.
PIC16F87XA FIGURE 18-15: AVERAGE WDT PERIOD vs. VDD OVER TEMPERATURE (-40°C TO +125°C) 50 45 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 40 125°C 35 WDT Period (ms) 85°C 30 25°C 25 20 -40°C 15 10 5 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-16: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 5V, -40°C TO +125°C) 5.5 5.0 4.5 4.0 Max 3.5 VOH (V) Typ (25°C) 3.0 2.5 Min 2.
PIC16F87XA FIGURE 18-17: TYPICAL, MINIMUM AND MAXIMUM VOH vs. IOH (VDD = 3V, -40°C TO +125°C) 3.5 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.0 2.5 Max VOH (V) 2.0 Typ (25°C) 1.5 Min 1.0 0.5 0.0 0 5 10 15 20 25 IOH (-mA) FIGURE 18-18: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 5V, -40°C TO +125°C) 1.0 0.
PIC16F87XA FIGURE 18-19: TYPICAL, MINIMUM AND MAXIMUM VOL vs. IOL (VDD = 3V, -40°C TO +125°C) 3.0 Max (125°C) Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 2.5 VOL (V) 2.0 1.5 Max (85°C) 1.0 Typ (25°C) 0.5 Min (-40°C) 0.0 0 5 10 15 20 25 IOL (-mA) FIGURE 18-20: MINIMUM AND MAXIMUM VIN vs. VDD (TTL INPUT, -40°C TO +125°C) 1.5 1.
PIC16F87XA FIGURE 18-21: MINIMUM AND MAXIMUM VIN vs. VDD (ST INPUT, -40°C TO +125°C) 4.0 Typical: statistical mean @ 25°C Maximum: mean + 3σ (-40°C to +125°C) Minimum: mean – 3σ (-40°C to +125°C) 3.5 VIH Max (125°C) 3.0 VIN (V) 2.5 VIH Min (-40°C) 2.0 VIL Max (-40°C) 1.5 1.0 VIL Min (125°C) 0.5 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V) FIGURE 18-22: MINIMUM AND MAXIMUM VIN vs. VDD (I2C INPUT, -40°C TO +125°C) 3.
PIC16F87XA FIGURE 18-23: A/D NONLINEARITY vs. VREFH (VDD = VREFH, -40°C TO +125°C) 4 3.5 Differential or Integral Nonlinearity (LSB) -40°C -40C 3 +25°C 25C 2.5 +85°C 85C 2 1.5 1 0.5 +125°C 125C 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD and VREFH (V) FIGURE 18-24: A/D NONLINEARITY vs. VREFH (VDD = 5V, -40°C TO +125°C) 3 Differential or Integral Nonlinearilty (LSB) 2.5 2 1.5 Max +125°C) Max (-40°C (-40C toto125C) 1 Typ Typ (+25°C) (25C) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.
PIC16F87XA 19.0 PACKAGING INFORMATION 19.1 Package Marking Information 40-Lead PDIP Example XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXX YYWWNNN 44-Lead TQFP XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 44-Lead PLCC XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN Legend: XX...
PIC16F87XA Package Marking Information (Cont’d) 44-Lead QFN XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN 28-Lead PDIP (Skinny DIP) Example PIC16F877A -I/ML 0310017 Example PIC16F876A/SP 0310017 XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SOIC XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN 28-Lead QFN XXXXXXXX XXXXXXXX YYWWNNN DS39582B-page 210 Example PIC16F876A/SO 0310017 Example PIC16F876A/ SS 0310017 Example 16F873A
PIC16F87XA 40-Lead Plastic Dual In-line (P) – 600 mil (PDIP) E1 D α 2 1 n E A2 A L c β B1 A1 eB p B Units Dimension Limits n p MIN INCHES* NOM 40 .100 .175 .150 MAX MILLIMETERS NOM 40 2.54 4.06 4.45 3.56 3.81 0.38 15.11 15.24 13.46 13.84 51.94 52.26 3.05 3.30 0.20 0.29 0.76 1.27 0.36 0.46 15.75 16.51 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .160 .190 Molded Package Thickness A2 .140 .160 Base to Seating Plane .015 A1 Shoulder to Shoulder Width E .595 .600 .
PIC16F87XA 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.
PIC16F87XA 44-Lead Plastic Leaded Chip Carrier (L) – Square (PLCC) E E1 #leads=n1 D1 D n 1 2 CH2 x 45 ° CH1 x 45 ° α A3 A2 35° A B1 B c β E2 Units Dimension Limits n p A1 p D2 INCHES* MIN NOM 44 .050 11 .165 .173 .145 .153 .020 .028 .024 .029 .040 .045 .000 .005 .685 .690 .685 .690 .650 .653 .650 .653 .590 .620 .590 .620 .008 .011 .026 .029 .013 .020 0 5 0 5 MAX MILLIMETERS NOM 44 1.27 11 4.19 4.39 3.68 3.87 0.51 0.71 0.61 0.74 1.02 1.14 0.00 0.13 17.40 17.53 17.40 17.53 16.51 16.59 16.51 16.
PIC16F87XA 44-Lead Plastic Quad Flat No Lead Package (ML) 8x8 mm Body (QFN) EXPOSED METAL PAD E p D D2 2 1 B n PIN 1 INDEX ON EXPOSED PAD OPTIONAL PIN 1 INDEX ON TOP MARKING E2 L TOP VIEW BOTTOM VIEW A A1 A3 Number of Pins Pitch Overall Height Standoff Base Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Lead Width Lead Length Units Dimension Limits n p A A1 A3 E E2 D D2 B L MIN .031 .000 .262 .262 .012 .014 INCHES NOM 44 .026 BSC .035 .001 .010 REF .315 BSC .
PIC16F87XA 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c β B1 A1 eB Units Number of Pins Pitch p B Dimension Limits n p INCHES* MIN NOM MILLIMETERS MAX MIN NOM 28 MAX 28 .100 2.54 Top to Seating Plane A .140 .150 .160 3.56 3.81 4.06 Molded Package Thickness A2 .125 .130 .135 3.18 3.30 3.43 8.26 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .310 .325 7.62 7.87 Molded Package Width E1 .275 .285 .295 6.
PIC16F87XA 28-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E E1 p D B 2 1 n h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Top Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L φ c B α β A1 MIN .093 .088 .004 .394 .288 .695 .010 .
PIC16F87XA 28-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α A c A2 φ A1 L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .396 .022 .004 0 .
PIC16F87XA 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body, Punch Singulated (QFN) EXPOSED METAL PADS E E1 Q D1 D D2 p 2 1 B n R E2 CH X 45° TOP VIEW L BOTTOM VIEW α A2 A A1 A3 Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff Base Thickness Overall Width Molded Package Width Exposed Pad Width Overall Length Molded Package Length Exposed Pad Length Lead Width Lead Length Tie Bar Width Tie Bar Length Chamfer Mold Draft Angle Top A A
PIC16F87XA APPENDIX A: REVISION HISTORY Revision A (November 2001) Original data sheet for PIC16F87XA devices. The devices presented are enhanced versions of the PIC16F87X microcontrollers discussed in the “PIC16F87X Data Sheet” (DS30292). APPENDIX B: DEVICE DIFFERENCES The differences between the devices in this data sheet are listed in Table B-1. Revision B (October 2003) This revision includes the DC and AC Characteristics Graphs and Tables. The Electrical Specifications in Section 17.
PIC16F87XA APPENDIX C: CONVERSION CONSIDERATIONS Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1.
PIC16F87XA INDEX A A/D ................................................................................... 127 Acquisition Requirements ........................................ 130 ADCON0 Register .................................................... 127 ADCON1 Register .................................................... 127 ADIF Bit .................................................................... 129 ADRESH Register .................................................... 127 ADRESL Register ..............
PIC16F87XA Capture/Compare/PWM Requirements (CCP1 and CCP2) .................................................... 186 CCP. See Capture/Compare/PWM. CCP1CON Register ........................................................... 19 CCP2CON Register ........................................................... 19 CCPR1H Register ........................................................ 19, 63 CCPR1L Register ......................................................... 19, 63 CCPR2H Register ............................
PIC16F87XA I I/O Ports ............................................................................. 41 I2C Bus Data Requirements ............................................ 192 I2C Bus Start/Stop Bits Requirements ............................. 191 I2C Mode Registers .................................................................... 80 I2C Mode ............................................................................ 80 ACK Pulse ............................................................
PIC16F87XA MPLAB ICE 4000 High-Performance Universal In-Circuit Emulator ................................................... 169 MPLAB Integrated Development Environment Software .............................................. 167 MPLINK Object Linker/MPLIB Object Librarian ............... 168 MSSP ................................................................................. 71 I2C Mode. See I2C. SPI Mode ................................................................... 71 SPI Mode. See SPI.
PIC16F87XA Power-up Timer (PWRT) .................................................. 148 PR2 Register ................................................................ 20, 61 Prescaler, Timer0 Assignment (PSA Bit) ................................................ 23 Rate Select (PS2:PS0 Bits) ....................................... 23 PRO MATE II Universal Device Programmer .................. 169 Program Counter Reset Conditions ...................................................... 149 Program Memory ........
PIC16F87XA Special Function Registers ................................................ 19 Special Function Registers (SFRs) .................................... 19 Speed, Operating ................................................................. 1 SPI Mode ..................................................................... 71, 77 Associated Registers ................................................. 79 Bus Mode Compatibility ............................................. 79 Effects of a Reset ............
PIC16F87XA I2C Bus Data ............................................................ 191 I2C Bus Start/Stop Bits ............................................. 190 I2C Master Mode (Reception, 7-bit Address) ........... 103 I2C Master Mode (Transmission, 7 or 10-bit Address) ......................................... 102 I2C Slave Mode (Transmission, 10-bit Address) ........ 89 I2C Slave Mode (Transmission, 7-bit Address) .......... 87 I2C Slave Mode with SEN = 1 (Reception, 10-bit Address) ...................
PIC16F87XA W Wake-up from Sleep ................................................ 143, 156 Interrupts .......................................................... 149, 150 MCLR Reset ............................................................. 150 WDT Reset ............................................................... 150 Wake-up Using Interrupts ................................................ 156 Watchdog Timer Register Summary ................................................... 155 Watchdog Timer (WDT) .
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PIC16F87XA PIC16F87XA PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F87XA(1), PIC16F87XAT(2); VDD range 4.0V to 5.5V PIC16LF87XA(1), PIC16LF87XAT(2); VDD range 2.0V to 5.
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