Datasheet

 2002 Microchip Technology Inc. Preliminary DS39598C-page 91
PIC16F818/819
12.2 RESET
The PIC16F818/819 differentiates between various
kinds of RESET:
• Power-on Reset (POR)
•MCLR
Reset during normal operation
•MCLR Reset during SLEEP
• WDT Reset during normal operation
• WDT Wake-up during SLEEP
• Brown-out Reset (BOR)
Some registers are not affected in any RESET condi-
tion. Their status is unknown on POR and unchanged
in any other RESET. Most other registers are reset to a
“RESET state” on Power-on Reset (POR), on the
MCLR and WDT Reset, on MCLR Reset during
SLEEP, and Brown-out Reset (BOR). They are not
affected by a WDT Wake-up, which is viewed as the
resumption of normal operation. The TO
and PD bits
are set or cleared differently in different RESET situa-
tions, as indicated in Table 12-3. These bits are used in
software to determine the nature of the RESET. Upon
a POR, BOR, or wake-up from SLEEP, the CPU
requires approximately 5 - 10 µs to become ready for
code execution. This delay runs in parallel with any
other timers. See Table 12-4 for a full description of
RESET states of all registers.
A simplified block diagram of the on-chip RESET circuit
is shown in Figure 12-1.
FIGURE 12-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
S
R
Q
External
RESET
MCLR
VDD
OSC1
WDT
Module
V
DD Rise
Detect
OST/PWRT
INTRC
WDT
Time-out
Power-on Reset
OST
10-bit Ripple Counter
PWRT
Chip_Reset
10-bit Ripple Counter
Reset
Enable OST
Enable PWRT
SLEEP
Brown-out
Reset
BOREN
31.25 kHz