Datasheet

 2002 Microchip Technology Inc. Preliminary DS39598C-page 37
PIC16F818/819
4.5.3 OSCILLATOR CONTROL REGISTER
The OSCCON register (Register 4-2) controls several
aspects of the system clock’s operation.
The Internal Oscillator Select bits, IRCF2:IRCF0, select
the frequency output of the internal oscillator block that
is used to drive the system clock. The choices are the
INTRC source (31.25 kHz), the INTOSC source
(8 MHz), or one of the six frequencies derived from the
INTOSC postscaler (125 kHz to 4 MHz). Changing the
configuration of these bits has an immediate change on
the internal oscillator’s output.
4.5.4 MODIFYING THE IRCF BITS
The IRCF bits can be modified at any time, regardless
of which clock source is currently being used as the
system clock. The internal oscillator allows users to
change the frequency during run time. This is achieved
by modifying the IRCF bits in the OSCCON register.
The sequence of events that occur after the IRCF bits
are modified is dependent upon the initial value of the
IRCF bits before they are modified. The system clock,
in either case, will switch to the new internal oscillator
frequency after eight falling edges of the new clock. If
the INTRC (31.25 kHz) is running and the IRCF bits are
modified to any of the other high frequency values, a
1 ms clock switch delay is turned on. Code execution
continues at a higher than expected frequency while
the new frequency stabilizes. Time sensitive code
should wait for the IOFS bit in the OSCCON register to
become set before continuing. The user can monitor
this bit to ensure that the frequency is stable before
using the system clock in time critical applications.
If the IRCF bits are modified while the internal oscillator
is running at any other frequency than INTRC
(31.25 kHz), there is no need for a 1 ms clock switch
delay. The new INTOSC frequency will be stable imme-
diately after the eight falling edges. The IOFS bit will
remain set after clock switching occurs.
Caution must be taken when modifying the IRCF bits
using BCF or BSF instructions. It is possible to modify
the IRCF bits to a frequency that may be out of the V
DD
specification range; for example, VDD = 2.0V and
IRCF = 111 (8 MHz).
4.5.5 CLOCK TRANSITION SEQUENCE
WHEN THE IRCF BITS ARE
MODIFIED
The following sequence is performed when the IRCF
bits are changed and the system clock is the internal
oscillator.
1. The IRCF bits are modified.
2. The clock switching circuitry waits for a falling
edge of the current clock, at which point CLKO
is held low.
3. The clock switching circuitry then waits for eight
falling edges of requested clock, after which it
switches CLKO to this new clock source.
4. If the INTRC (31.25 kHz) is enabled, the IOFS
bit is clear to indicate that the clock is unstable
and a 1 ms delay is started. If the internal oscil-
lator frequency is anything other than INTRC
(31.25 kHz), this step is skipped. After the
appropriate number of clock periods have
passed, the IOFS bit is set to indicate to the
internal oscillator that the frequency is stable.
5. Oscillator switch over is complete.