Datasheet
PIC16F818/819
DS39598C-page 32 Preliminary 2002 Microchip Technology Inc.
3.8 Protection Against Spurious Write
There are conditions when the device should not write
to the data EEPROM memory. To protect against spu-
rious EEPROM writes, various mechanisms have been
built-in. On power-up, WREN is cleared. Also, the
Power-up Timer (72 ms duration) prevents an
EEPROM write.
The write initiate sequence and the WREN bit together,
help prevent an accidental write during brown-out,
power glitch, or software malfunction.
3.9 Operation During Code Protect
When the data EEPROM is code protected, the micro-
controller can read and write to the EEPROM normally.
However, all external access to the EEPROM is dis-
abled. External write access to the program memory is
also disabled.
When program memory is code protected, the micro-
controller can read and write to program memory nor-
mally, as well as execute instructions. Writes by the
device may be selectively inhibited to regions of the
memory, depending on the setting of bits WRT1:WRT0
of the configuration word (see Section 12.1 for addi-
tional information). External access to the memory is
also disabled.
TABLE 3-1: REGISTERS/BITS ASSOCIATED WITH DATA EEPROM AND
FLASH PROGRAM MEMORIES
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
Power-on
Reset
Value on
all other
RESETS
10Ch EEDATA EEPROM/FLASH Data Register Low Byte xxxx xxxx uuuu uuuu
10Dh EEADR EEPROM/FLASH Address Register Low Byte xxxx xxxx uuuu uuuu
10Eh EEDATH
— — EEPROM/FLASH Data Register High Byte --xx xxxx --uu uuuu
10Fh EEADRH
— — — — — EEPROM/FLASH Address
Register High Byte
---- -xxx ---- -uuu
18Ch EECON1 EEPGD
— — FREE WRERR WREN WR RD x--x x000 x--x q000
18Dh EECON2 EEPROM Control Register2 (not a physical register) ---- ---- ---- ----
0Dh PIR2
— — — EEIF — — — — ---0 ---- ---0 ----
8Dh PIE2
— — —EEIE— — — — ---0 ---- ---0 ----
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0', q = value depends upon condition.
Shaded cells are not used by Data EEPROM or FLASH Program Memory.