Datasheet

 2002 Microchip Technology Inc. Preliminary DS39598C-page 21
PIC16F818/819
2.2.2.6 PIE2 Register
The PIE2 register contains the individual enable bit for
the EEPROM write operation interrupt.
REGISTER 2-6: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ADDRESS 8Dh)
2.2.2.7 PIR2 Register
The PIR2 register contains the flag bit for the EEPROM
write operation interrupt.
.
REGISTER 2-7: PIR2: PERIPHERAL INTERRUPT FLAG REGISTER 2 (ADDRESS 0Dh)
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
— — — EEIE — — — —
bit 7 bit 0
bit 7-5 Unimplemented: Read as '0'
bit 4 EEIE: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown
Note: Interrupt flag bits are set when an interrupt
condition occurs, regardless of the state of
its corresponding enable bit, or the global
enable bit, GIE (INTCON<7>). User soft-
ware should ensure the appropriate inter-
rupt flag bits are clear prior to enabling an
interrupt.
U-0 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0
— — — EEIF — — — —
bit 7 bit 0
bit 7-5 Unimplemented: Read as '0'
bit 4 EEIF: EEPROM Write Operation Interrupt Enable bit
1 = Enable EE Write Interrupt
0 = Disable EE Write Interrupt
bit 3-0 Unimplemented: Read as '0'
Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
- n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown