PIC16F818/819 Data Sheet 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology 2002 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature.
PIC16F818/819 18/20-Pin Enhanced FLASH Microcontrollers with nanoWatt Technology Low Power Features: Pin Diagram • Power Managed modes: - Primary RUN XT, RC oscillator, 87 µA, 1 MHz, 2V - INTRC 7 µA, 31.25 kHz, 2V - SLEEP 0.2 µA, 2V • Timer1 oscillator 1.3 µA, 32 kHz, 2V • Watchdog Timer 0.7 µA, 2V • Wide operating voltage range: - Industrial: 2.0V to 5.
PIC16F818/819 Pin Diagrams DS39598C-page 2 RA1/AN1 RA0/AN0 NC 23 22 NC 25 24 RA3/AN3/VREF+ RA2/AN2/VREF- RA4/AN4/T0CKI 28 28-pin QFN •1 2 3 4 5 6 7 8 9 10 RA2/AN2/VREFRA3/AN3/VREF+ RA4/AN4/T0CKI RA5/MCLR/VPP VSS VSS RB0/INT RB1/SDI/SDA RB2/SDO/CCP1 RB3/CCP1/PGM RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD RB7/T1OSI/PGD RB6/T1OSO/T1CKI/PGC RB5/SS RB4/SCK/SCL 26 18 17 16 15 14 13 12 11 10 27 20 19 18 17 16 15 14 13 12 11 RA1/AN1 RA0/AN0 RA7/OSC1/CLKI RA6/OSC2/CLKO VDD VDD RB7/T1OSI/PGD
PIC16F818/819 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Memory Organization ................................................................................................................................................................... 9 3.0 Data EEPROM and FLASH Program Memory.........................................................
PIC16F818/819 NOTES: DS39598C-page 4 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 1.0 DEVICE OVERVIEW TABLE 1-1: This document contains device specific information for the operation of the PIC16F818/819 devices. Additional information may be found in the PICmicroTM Mid-Range MCU Reference Manual (DS33023), which may be downloaded from the Microchip web site. The Reference Manual should be considered a complementary document to this data sheet, and is highly recommended reading for a better understanding of the device architecture and operation of the peripheral modules.
PIC16F818/819 FIGURE 1-1: PIC16F818/819 BLOCK DIAGRAM 13 FLASH Program Memory 1K/2K x 14 Program Bus RAM Addr(1) PORTB 9 Addr MUX Instruction reg 7 Direct Addr 8 Indirect Addr FSR reg STATUS reg 8 3 Power-up Timer Instruction Decode & Control Oscillator Start-up Timer Timing Generation Watchdog Timer Brown-out Reset MCLR RB0/INT RB1/SDI/SDA RB2/SDO/CCP1 RB3/CCP1/PGM RB4/SCK/SCL RB5/SS RB6/T1OSO/T1CKI/PGC RB7/T1OSI/PGD MUX 8 W reg VDD, VSS Timer0 Timer1 Timer2 10-bit, 5-channel A/D
PIC16F818/819 TABLE 1-2: Pin Name PIC16F818/819 PINOUT DESCRIPTIONS PDIP/ SSOP SOIC Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTA is a bi-directional I/O port. RA0/AN0 RA0 AN0 17 RA1/AN1 RA1 AN1 18 RA2/AN2/VREFRA2 AN2 VREF- 1 RA3/AN3/VREF+ RA3 AN3 VREF+ 2 RA4/AN4/T0CKI RA4 AN4 T0CKI 3 RA5/MCLR/VPP RA5 MCLR 4 19 20 1 2 3 4 23 15 17 16 18 Bi-directional I/O pin. Analog input channel 0. I/O I TTL Analog Bi-directional I/O pin. Analog input channel 1.
PIC16F818/819 TABLE 1-2: PIC16F818/819 PINOUT DESCRIPTIONS (CONTINUED) Pin Name PDIP/ SSOP SOIC Pin# Pin# QFN Pin# I/O/P Type Buffer Type Description PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs.
PIC16F818/819 2.0 MEMORY ORGANIZATION 2.1 There are two memory blocks in the PIC16F818/819. These are the program memory and the data memory. Each block has its own bus, so access to each block can occur during the same oscillator cycle. The data memory can be further broken down into the general purpose RAM and the Special Function Registers (SFRs). The operation of the SFRs that control the “core” are described here.
PIC16F818/819 2.2 Data Memory Organization The Data Memory is partitioned into multiple banks that contain the General Purpose Registers and the Special Function Registers. Bits RP1 (STATUS<6>) and RP0 (STATUS<5>) are the bank select bits. RP1:RP0 Bank 00 0 01 1 10 2 11 3 Each bank extends up to 7Fh (128 bytes). The lower locations of each bank are reserved for the Special Function Registers. Above the Special Function Registers are General Purpose Registers, implemented as static RAM.
PIC16F818/819 FIGURE 2-3: PIC16F818 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h General Purpose Register Indirect addr.
PIC16F818/819 FIGURE 2-4: PIC16F819 REGISTER FILE MAP File Address Indirect addr.(*) TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON PIR1 PIR2 TMR1L TMR1H T1CON TMR2 T2CON SSPBUF SSPCON CCPR1L CCPR1H CCP1CON ADRESH ADCON0 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h File Address Indirect addr.
PIC16F818/819 2.2.2 SPECIAL FUNCTION REGISTERS The Special Function Registers can be classified into two sets: core (CPU) and peripheral. Those registers associated with the core functions are described in detail in this section. Those related to the operation of the peripheral features are described in detail in the peripheral feature section. The Special Function Registers are registers used by the CPU and peripheral modules for controlling the desired operation of the device.
PIC16F818/819 TABLE 2-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 1 80h(1) INDF 81h OPTION 82h(1) PCL 83h(1) STATUS Addressing this location uses contents of FSR to address data memory (not a physical register) RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 PD Z DC C Program Counter's (PC) Least Significant Byte IRP RP1 RP0 TO 84h(1) FSR Indirect Data Memory Address Pointer
PIC16F818/819 TABLE 2-1: Address Name SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR Details on page: Bank 2 100h(1) INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 23 101h TMR0 Timer0 Module’s Register xxxx xxxx 53 102h(1 PCL Program Counter's (PC) Least Significant Byte 0000 0000 23 (1) STATUS (1) FSR 103h 104h 105h — 106h IRP RP1 RP0 TO PD
PIC16F818/819 2.2.2.1 STATUS Register The STATUS register, shown in Register 2-1, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC or C bits, then the write to these three bits is disabled. These bits are set or cleared according to the device logic.
PIC16F818/819 2.2.2.2 OPTION Register Note: The OPTION register is a readable and writable register that contains various control bits to configure the TMR0 prescaler/WDT postscaler (single assignable register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB. REGISTER 2-2: To achieve a 1:1 prescaler assignment for the TMR0 register, assign the prescaler to the Watchdog Timer.
PIC16F818/819 2.2.2.3 INTCON Register The INTCON Register is a readable and writable register that contains various enable and flag bits for the TMR0 register overflow, RB port change and external RB0/INT pin interrupts. REGISTER 2-3: Note: Interrupt flag bits get set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>).
PIC16F818/819 2.2.2.4 PIE1 Register This register contains the individual enable bits for the peripheral interrupts. Note: Bit PEIE (INTCON<6>) must be set to enable any peripheral interrupt.
PIC16F818/819 2.2.2.5 PIR1 Register Note: This register contains the individual flag bits for the Peripheral interrupts. REGISTER 2-5: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit, or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
PIC16F818/819 2.2.2.6 PIE2 Register The PIE2 register contains the individual enable bit for the EEPROM write operation interrupt.
PIC16F818/819 2.2.2.8 Note: PCON Register Note: Interrupt flag bits get set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. BOR is unknown on Power-on Reset. It must then be set by the user and checked on subsequent RESETS to see if BOR is clear, indicating a brown-out has occurred.
PIC16F818/819 2.3 PCL and PCLATH The program counter (PC) is 13 bits wide. The low byte comes from the PCL register, which is a readable and writable register. The upper bits (PC<12:8>) are not readable, but are indirectly writable through the PCLATH register. On any RESET, the upper bits of the PC will be cleared. Figure 2-5 shows the two situations for the loading of the PC. The upper example in the figure shows how the PC is loaded on a write to PCL (PCLATH<4:0> → PCH).
PIC16F818/819 FIGURE 2-6: DIRECT/INDIRECT ADDRESSING Direct Addressing RP1:RP0 Bank Select 6 Indirect Addressing From Opcode 0 IRP 7 FSR Register Bank Select Location Select 00 01 10 0 Location Select 11 00h 80h 100h 180h 7Fh FFh 17Fh 1FFh Data Memory(1) Bank 0 Note 1: Bank 1 Bank 2 Bank 3 For register file map detail, see Figure 2-3 or Figure 2-4. DS39598C-page 24 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 3.0 DATA EEPROM AND FLASH PROGRAM MEMORY 3.1 The Data EEPROM and FLASH Program memory is readable and writable during normal operation (over the full VDD range). This memory is not directly mapped in the register file space. Instead, it is indirectly addressed through the Special Function Registers.
PIC16F818/819 REGISTER 3-1: EECON1: EEPROM ACCESS CONTROL REGISTER 1 (ADDRESS 18Ch) R/W-x U-0 U-0 R/W-x R/W-x R/W-0 R/S-0 R/S-0 EEPGD — — FREE WRERR WREN WR RD bit 7 bit 0 bit 7 EEPGD: Program/Data EEPROM Select bit 1 = Accesses program memory 0 = Accesses data memory Reads ‘0’ after a POR; this bit cannot be changed while a write operation is in progress.
PIC16F818/819 3.3 Reading Data EEPROM Memory To read a data memory location, the user must write the address to the EEADR register, clear the EEPGD control bit (EECON1<7>) and then set control bit, RD (EECON1<0>). The data is available in the very next cycle, in the EEDATA register; therefore, it can be read in the next instruction (see Example 3-1). EEDATA will hold this value until another read, or until it is written to by the user (during a write operation).
PIC16F818/819 3.5 Reading FLASH Program Memory 3.6 Erasing FLASH Program Memory To read a program memory location, the user must write two bytes of the address to the EEADR and EEADRH registers, set the EEPGD control bit (EECON1<7>), and then set control bit RD (EECON1<0>). Once the read control bit is set, the program memory FLASH controller will use the second instruction cycle to read the data. This causes the second instruction immediately following the “BSF EECON1,RD” instruction to be ignored.
PIC16F818/819 EXAMPLE 3-4: ERASING A FLASH PROGRAM MEMORY ROW BANKSEL EEADRH MOVF ADDRH, W MOVWF EEADRH MOVF ADDRL, W MOVWF EEADR ; Select Bank of EEADRH ; ; MS Byte of Program Address to Erase ; ; LS Byte of Program Address to Erase ERASE_ROW BANKSEL EECON1 ; Select Bank of EECON1 BSF EECON1, EEPGD; Point to PROGRAM memory BSF EECON1, WREN ; Enable Write to memory BSF EECON1, FREE ; Enable Row Erase operation ; BCF MOVLW MOVWF MOVLW MOVWF BSF NOP NOP BCF BSF INTCON, GIE 55h EECON2 AAh EECON2 EECON1, W
PIC16F818/819 3.7 Writing to FLASH Program Memory There are 4 buffer register words and all four locations MUST be written to with correct data. FLASH program memory may only be written to if the destination address is in a segment of memory that is not write protected, as defined in bits WRT1:WRT0 of the device configuration word (Register 12-1). FLASH program memory must be written in four-word blocks.
PIC16F818/819 An example of the complete four-word write sequence is shown in Example 3-5. The initial address is loaded into the EEADRH:EEADR register pair; the four words of data are loaded using indirect addressing, assuming that a row erase sequence has already been performed. EXAMPLE 3-5: WRITING TO FLASH PROGRAM MEMORY ; This write routine assumes the following: ; ; ; ; ; ; 1. 2. 3. 4. 5. 6. The 32 words in the erase block have already been erased.
PIC16F818/819 3.8 Protection Against Spurious Write 3.9 There are conditions when the device should not write to the data EEPROM memory. To protect against spurious EEPROM writes, various mechanisms have been built-in. On power-up, WREN is cleared. Also, the Power-up Timer (72 ms duration) prevents an EEPROM write. When the data EEPROM is code protected, the microcontroller can read and write to the EEPROM normally. However, all external access to the EEPROM is disabled.
PIC16F818/819 4.0 OSCILLATOR CONFIGURATIONS 4.1 Oscillator Types TABLE 4-1: The PIC16F818/819 can be operated in eight different Oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these eight modes (modes 5 - 8 are new PIC16 oscillator configurations): 1. 2. 3. 4. LP XT HS RC 5. RCIO 6. INTIO1 7. INTIO2 8. ECIO 4.
PIC16F818/819 FIGURE 4-2: CERAMIC RESONATOR OPERATION (HS OR XT OSC CONFIGURATION) OSC1 PIC16F818/819 C1(1) RES RF(3) RS External Clock Input The ECIO Oscillator mode requires an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset, or after an exit from SLEEP mode. In the ECIO Oscillator mode, the OSC2 pin becomes an additional general purpose I/O pin. The I/O pin becomes bit 6 of PORTA (RA6).
PIC16F818/819 4.4 RC Oscillator 4.5 For timing insensitive applications, the “RC” and “RCIO” device options offer additional cost savings. The RC oscillator frequency is a function of the supply voltage, the resistor (REXT) and capacitor (CEXT) values, and the operating temperature. In addition to this, the oscillator frequency will vary from unit to unit due to normal manufacturing variation.
PIC16F818/819 4.5.1 INTRC MODES 4.5.2 Using the internal oscillator as the clock source can eliminate the need for up to two external oscillator pins, which can then be used for digital I/O. Two distinct configurations are available: • In INTIO1 mode, the OSC2 pin outputs FOSC/4, while OSC1 functions as RA7 for digital input and output. • In INTIO2 mode, OSC1 functions as RA7 and OSC2 functions as RA6, both for digital input and output.
PIC16F818/819 4.5.3 OSCILLATOR CONTROL REGISTER 4.5.5 The OSCCON register (Register 4-2) controls several aspects of the system clock’s operation. The Internal Oscillator Select bits, IRCF2:IRCF0, select the frequency output of the internal oscillator block that is used to drive the system clock. The choices are the INTRC source (31.25 kHz), the INTOSC source (8 MHz), or one of the six frequencies derived from the INTOSC postscaler (125 kHz to 4 MHz).
PIC16F818/819 FIGURE 4-6: PIC16F818/819 CLOCK DIAGRAM PIC18F818/819 CONFIG (FOSC2:FOSC0) OSC2 SLEEP LP, XT, HS, RC, EC OSCCON<6:4> 4 MHz Internal Oscillator Block 8 MHz (INTOSC) bit 3 bit 2 bit 1-0 31.
PIC16F818/819 5.0 I/O PORTS Pin RA4 is multiplexed with the Timer0 module clock input and with analog input to become the RA4/AN4/ T0CKI pin. The RA4/AN4/T0CKI pin is a Schmitt Trigger input and full CMOS output driver. Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Pin RA5 is multiplexed with the Master Clear module input.
PIC16F818/819 FIGURE 5-1: BLOCK DIAGRAM OF RA0/AN0:RA1/AN1 PINS FIGURE 5-3: Data Bus Data Bus D WR PORTA Q CK Q D WR PORTA VDD VDD P CK CK Q I/O pin Analog Input Mode Q N WR TRISA CK Q I/O pin VSS VSS Analog Input Mode VSS TTL Input Buffer RD TRISA Q TRIS Latch VSS TRIS Latch VDD VDD P Q D Q N WR TRISA Q Data Latch Data Latch D BLOCK DIAGRAM OF RA2/AN2/VREF- PIN TTL Input Buffer RD TRISA Q D D EN EN RD PORTA RD PORTA To A/D Module VREF- Input To A/D Module Channel
PIC16F818/819 FIGURE 5-5: BLOCK DIAGRAM OF RA5/MCLR/VPP PIN MCLRE Schmitt Trigger Buffer MCLR Circuit MCLR Filter Data Bus RA5/MCLR/VPP Schmitt Trigger Input Buffer RD TRIS VSS Q VSS D EN MCLRE RD Port FIGURE 5-6: BLOCK DIAGRAM OF RA6/OSC2/CLKO PIN From OSC1 Oscillator Circuit CLKO (FOSC/4) VDD VDD P RA6/OSC2/CLKO Data Bus D WR PORTA VSS N (FOSC = 1x1) Q VSS VDD Q CK P Data Latch D WR TRISA Q N CK Q (FOSC = 1x0,011) TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D E
PIC16F818/819 FIGURE 5-7: BLOCK DIAGRAM OF RA7/OSC1/CLKI PIN From OSC2 Oscillator Circuit VDD (FOSC = 011) Data Bus D WR PORTA CK Q VDD Q P RA7/OSC1/CLKI VSS Data Latch D WR TRISA Q CK N Q FOSC = 10x TRIS Latch VSS Schmitt Trigger Input Buffer RD TRISA Q D EN FOSC = 10x RD PORTA Note 1: I/O pins have protection diodes to VDD and VSS. DS39598C-page 42 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 5.2 PORTB and the TRISB Register PORTB is an 8-bit wide, bi-directional port. The corresponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a Hi-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). Each of the PORTB pins has a weak internal pull-up.
PIC16F818/819 TABLE 5-3: PORTB FUNCTIONS Name Bit# Buffer Function TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. (5) Input/output pin, SPI Data input pin or I2C Data I/O pin. RB1/SDI/SDA bit 1 TTL/ST Internal software programmable weak pull-up. (4) Input/output pin, SPI Data output pin or RB2/SDO/CCP1 bit 2 TTL/ST Capture input/Compare output/PWM output pin. Internal software programmable weak pull-up.
PIC16F818/819 FIGURE 5-8: BLOCK DIAGRAM OF RB0 PIN VDD RBPU(2) Weak P Pull-up Data Latch D Q Data Bus WR PORTB I/O pin(1) CK TRIS Latch D Q WR TRISB TTL Input Buffer CK RD TRISB Q RD PORTB D EN To INT0 or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2002 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-9: BLOCK DIAGRAM OF RB1 PIN I2C Mode PORT/SSPEN Select SDA Output 1 0 VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up VDD Data Latch D Q P CK N I/O pin(1) VSS TRIS Latch D Q WR TRISB CK Q RD TRISB TTL Input Buffer SDA Drive Q RD PORTB D EN Schmitt Trigger Buffer RD PORTB SDA(3) SDI Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-10: BLOCK DIAGRAM OF RB2 PIN CCPMX Module Select SDO 0 0 CCP 1 1 VDD RBPU(2) Data Bus WR PORTB WR TRISB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q TTL Input Buffer CK RD TRISB D Q RD PORTB EN RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2002 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-11: BLOCK DIAGRAM OF RB3 PIN CCP1 = 1000,1001,11xx and CCPMX = 0 CCP1 = 0100, 0101, 0110, 0111 and CCPMX = 0 CCP 0 or LVP = 1 1 VDD RBPU(2) Data Bus WR PORTB WR TRISB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch D Q TTL Input Buffer CK RD TRISB Q RD PORTB D EN To PGM or CCP RD PORTB Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-12: BLOCK DIAGRAM OF RB4 PIN PORT/SSPEN SCK/SCL 1 0 VDD RBPU(2) Weak P Pull-up VDD SCL Drive Data Bus WR PORTB P Data Latch D Q I/O pin(1) N CK TRIS Latch WR TRISB D VSS Q CK TTL Input Buffer RD TRISB Latch Q Set RBIF D EN RD PORTB Q From Other RB7:RB4 pins D EN Q1 RD PORTB Q3 SCK SCL(3) Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit.
PIC16F818/819 FIGURE 5-13: BLOCK DIAGRAM OF RB5 PIN RBPU(2) VDD PORT/SSPEN Weak P Pull-up Data Latch Data Bus D WR PORTB Q I/O pin(1) CK TRIS Latch D WR TRISB Q CK TTL Input Buffer RD TRISB Latch Q EN RD PORTB Set RBIF D Q From Other RB7:RB4 pins D EN Q1 RD PORTB Q3 SS Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. DS39598C-page 50 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-14: BLOCK DIAGRAM OF RB6 PIN VDD RBPU(2) Data Bus WR PORTB Weak P Pull-up Data Latch D Q I/O pin(1) CK TRIS Latch WR TRISB D Q CK T1OSCEN RD TRISB T1OSCEN/ICD/PROG Mode TTL Input Buffer Latch Q D EN RD PORTB Q1 Set RBIF Q From Other RB7:RB4 pins D EN RD PORTB Q3 PGC/T1CKI From T1OSCO Output Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit. 2002 Microchip Technology Inc.
PIC16F818/819 FIGURE 5-15: BLOCK DIAGRAM OF RB7 PIN PORT/Program Mode/ICD PGD 1 0 VDD RBPU(2) Weak P Pull-up Data Latch Data Bus D WR PORTB Q I/O pin(1) CK TRIS Latch D WR TRISB Q 0 CK 1 RD TRISB T1OSCEN T1OSCEN Analog Input Mode PGD DRVEN TTL Input Buffer Latch Q D EN RD PORTB Q1 Set RBIF Q From Other RB7:RB4 pins D EN RD PORTB Q3 PGD To T1OSCI Input Note 1: I/O pins have diode protection to VDD and VSS.
PIC16F818/819 6.0 TIMER0 MODULE increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Timer0 module timer/counter has the following features: • • • • • • Counter mode is selected by setting bit T0CS (OPTION<5>). In Counter mode, Timer0 will increment, either on every rising or falling edge of pin RA4/ T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit T0SE (OPTION<4>).
PIC16F818/819 6.3 Using Timer0 with an External Clock 6.4 When no prescaler is used, the external clock input is the same as the prescaler output. The synchronization of T0CKI, with the internal phase clocks, is accomplished by sampling the prescaler output on the Q2 and Q4 cycles of the internal phase clocks. Therefore, it is necessary for T0CKI to be high for at least 2 TOSC (and a small RC delay of 20 ns) and low for at least 2 TOSC (and a small RC delay of 20 ns).
PIC16F818/819 EXAMPLE 6-1: BANKSEL MOVLW MOVWF BANKSEL CLRF BANKSEL MOVLW MOVWF CLRWDT MOVLW MOVWF CHANGING THE PRESCALER ASSIGNMENT FROM TIMER0 TO WDT OPTION b'xx0x0xxx' OPTION TMR0 TMR0 OPTION b'xxxx1xxx' OPTION CHANGING THE PRESCALER ASSIGNMENT FROM WDT TO TIMER0 CLRWDT BANKSEL OPTION MOVLW b'xxxx0xxx' MOVWF OPTION TABLE 6-1: 01h,101h ; ; ; ; Clear WDT and prescaler Select Bank of OPTION Select TMR0, new prescale value and clock source REGISTERS ASSOCIATED WITH TIMER0 Name TMR0 0Bh,8Bh, INTCON
PIC16F818/819 NOTES: DS39598C-page 56 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 7.0 TIMER1 MODULE The Timer1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMR1H and TMR1L), which are readable and writable. The TMR1 Register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The TMR1 Interrupt, if enabled, is generated on overflow, which is latched in interrupt flag bit TMR1IF (PIR1<0>). This interrupt can be enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE (PIE1<0>).
PIC16F818/819 7.2 Timer1 Operation in Timer Mode 7.4 Timer mode is selected by clearing the TMR1CS (T1CON<1>) bit. In this mode, the input clock to the timer is FOSC/4. The synchronize control bit T1SYNC (T1CON<2>) has no effect, since the internal clock is always in sync. 7.3 Counter mode is selected by setting bit TMR1CS. In this mode, the timer increments on every rising edge of clock input on pin RB7/T1OSI/PGD, when bit T1OSCEN is set, or on pin RB6/T1OSO/T1CKI/PGC, when bit T1OSCEN is cleared.
PIC16F818/819 7.5 Timer1 Operation in Asynchronous Counter Mode 7.5.1 If control bit T1SYNC (T1CON<2>) is set, the external clock input is not synchronized. The timer continues to increment asynchronous to the internal phase clocks. The timer will continue to run during SLEEP and can generate an interrupt on overflow, that will wake-up the processor. However, special precautions in software are needed to read/write the timer (Section 7.5.1).
PIC16F818/819 7.6 Timer1 Oscillator 7.7 A crystal oscillator circuit is built between pins T1OSI (input) and T1OSO (amplifier output). It is enabled by setting control bit T1OSCEN (T1CON<3>). The oscillator is a low power oscillator rated up to 32.768 kHz. It will continue to run during SLEEP. It is primarily intended for a 32 kHz crystal. The circuit for a typical LP oscillator is shown in Figure 7-3. Table 7-1 shows the capacitor selection for the Timer1 oscillator.
PIC16F818/819 7.9 Resetting Timer1 Register Pair (TMR1H, TMR1L) 7.11 TMR1H and TMR1L registers are not reset to 00h on a POR, or any other RESET, except by the CCP1 special event triggers. T1CON register is reset to 00h on a Power-on Reset or a Brown-out Reset, which shuts off the timer and leaves a 1:1 prescale. In all other RESETS, the register is unaffected. 7.10 Timer1 Prescaler The prescaler counter is cleared on writes to the TMR1H or TMR1L registers.
PIC16F818/819 EXAMPLE 7-3: RTCinit banksel movlw movwf clrf movlw movwf clrf clrf movlw movwf banksel bsf return banksel bsf bcf incf movf sublw btfss return clrf incf movf sublw btfss return clrf incf movf sublw btfss return clrf return RTCisr TABLE 7-2: Address IMPLEMENTING A REAL-TIME CLOCK USING A TIMER1 INTERRUPT SERVICE TMR1H 0x80 TMR1H TMR1L b’00001111’ T1CON secs mins .12 hours PIE1 PIE1, TMR1IE TMR1H TMR1H,7 PIR1,TMR1IF secs,F secs,w .
PIC16F818/819 8.0 TIMER2 MODULE 8.1 Timer2 is an 8-bit timer with a prescaler and a postscaler. It can be used as the PWM time-base for the PWM mode of the CCP1 module. The TMR2 register is readable and writable, and is cleared on any device RESET. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits T2CKPS1:T2CKPS0 (T2CON<1:0>). The Timer2 module has an 8-bit period register, PR2.
PIC16F818/819 REGISTER 8-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 — R/W-0 R/W-0 TOUTPS3 TOUTPS2 R/W-0 R/W-0 TOUTPS1 R/W-0 R/W-0 R/W-0 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 bit 7 bit 0 bit 7 Unimplemented: Read as ‘0’ bit 6-3 TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale 0010 = 1:3 Postscale • • • 1111 = 1:16 Postscale bit 2 TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0 T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select b
PIC16F818/819 9.0 CAPTURE/COMPARE/PWM (CCP) MODULE The CCP module’s input/output pin (CCP1) can be configured as RB2 or RB3. This selection is set in bit 12 (CCPMX) of the configuration word. The Capture/Compare/PWM (CCP) module contains a 16-bit register that can operate as a: • 16-bit capture register • 16-bit compare register • PWM master/slave duty cycle register. Table 9-1 shows the timer resources of the CCP module modes.
PIC16F818/819 9.1 Capture Mode 9.1.2 In Capture mode, CCPR1H:CCPR1L captures the 16-bit value of the TMR1 register when an event occurs on CCP1 pin. An event is defined as: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 9.1.1 CCP PIN CONFIGURATION In Capture mode, the CCP1 pin should be configured as an input by setting the TRISB bit Note 1: If the CCP1 pin is configured as an output, a write to the port can cause a capture condition.
PIC16F818/819 9.2 Compare Mode 9.2.1 The user must configure the CCP1 pin as an output by clearing the TRISB bit. In Compare mode, the 16-bit CCPR1 register value is constantly compared against the TMR1 register pair value. When a match occurs, the CCP1 pin is: Note 1: Clearing the CCP1CON register will force the CCP1 compare output latch to the default low level. This is not the data latch.
PIC16F818/819 9.3 PWM Mode 9.3.1 In Pulse Width Modulation (PWM) mode, the CCP1 pin produces up to a 10-bit resolution PWM output. Since the CCP1 pin is multiplexed with the PORTB data latch, the TRISB bit must be cleared to make the CCP1 pin an output. Note: Clearing the CCP1CON register will force the CCP1 PWM output latch to the default low level. This is not the PORTB I/O data latch. Figure 9-3 shows a simplified block diagram of the CCP module in PWM mode.
PIC16F818/819 9.3.3 The maximum PWM resolution (bits) for a given PWM frequency is given by the following formula. The following steps should be taken when configuring the CCP module for PWM operation: EQUATION 9-3: Resolution Note: ( FOSC log FPWM = log(2) ) SETUP FOR PWM OPERATION 1. 2. bits Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. Make the CCP1 pin an output by clearing the TRISB bit.
PIC16F818/819 NOTES: DS39598C-page 70 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 10.0 10.1 SYNCHRONOUS SERIAL PORT (SSP) MODULE SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, display drivers, A/D converters, etc.
PIC16F818/819 REGISTER 10-1: SSPSTAT: SYNCHRONOUS SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/A P S R/W UA BF bit 7 bit 0 bit 7 SMP: SPI Data Input Sample Phase bit SPI Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time (Microwire®) SPI Slave mode: This bit must be cleared when SPI is used in Slave mode I2 C mode: This bit must be maintained clear bit 6 CKE: SPI Clock Edge Selec
PIC16F818/819 REGISTER 10-2: SSPCON: SYNCHRONOUS SERIAL PORT CONTROL REGISTER 1 (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 bit 7 bit 0 bit 7 WCOL: Write Collision Detect bit 1 = An attempt to write the SSPBUF register failed because the SSP module is busy (must be cleared in software) 0 = No collision bit 6 SSPOV: Receive Overflow Indicator bit In SPI mode: 1 = A new byte is received while the SSPBUF register is still hold
PIC16F818/819 FIGURE 10-1: SSP BLOCK DIAGRAM (SPI MODE) To enable the serial port, SSP enable bit SSPEN (SSPCON<5>) must be set. To reset or reconfigure SPI mode, clear bit SSPEN, re-initialize the SSPCON register, and then set bit SSPEN. This configures the SDI, SDO, SCK, and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISB register) appropriately programmed.
PIC16F818/819 FIGURE 10-2: SPI MODE TIMING, MASTER MODE SCK (CKP = 0, CKE = 0) SCK (CKP = 0, CKE = 1) SCK (CKP = 1, CKE = 0) SCK (CKP = 1, CKE = 1) bit7 SDO bit6 bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SDI (SMP = 1) bit7 bit0 SSPIF FIGURE 10-3: SPI MODE TIMING (SLAVE MODE WITH CKE = 0) SS (Optional) SCK (CKP = 0) SCK (CKP = 1) bit7 SDO bit6 bit5 bit2 bit3 bit4 bit1 bit0 SDI (SMP = 0) bit7 bit0 SSPIF FIGURE 10-4: SPI MODE TIMING (SLAVE MODE WITH CKE = 1) SS SC
PIC16F818/819 10.3 SSP I 2C Mode Operation The SSP module in I 2C mode fully implements all slave functions, except general call support, and provides interrupts on START and STOP bits in hardware to facilitate firmware implementations of the master functions. The SSP module implements the standard mode specifications, as well as 7-bit and 10-bit addressing. Two pins are used for data transfer. These are the RB4/SCK/SCL pin, which is the clock (SCL), and the RB1/SDI/SDA pin, which is the data (SDA).
PIC16F818/819 10.3.1.1 Addressing 10.3.1.2 Once the SSP module has been enabled, it waits for a START condition to occur. Following the START condition, the eight bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the clock (SCL) line. The value of register SSPSR<7:1> is compared to the value of the SSPADD register. The address is compared on the falling edge of the eighth clock (SCL) pulse.
PIC16F818/819 TABLE 10-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received SSPSR → SSPBUF Generate ACK Pulse Set bit SSPIF (SSP Interrupt Occurs if Enabled) BF SSPOV 0 0 Yes Yes Yes 1 0 No No Yes 1 1 No No Yes 0 1 No No Yes Note 1: Shaded cells show the conditions where the user software did not properly clear the overflow condition.
PIC16F818/819 10.3.2 MASTER MODE OPERATION 10.3.3 Master mode operation is supported in firmware using interrupt generation on the detection of the START and STOP conditions. The STOP (P) and START (S) bits are cleared from a RESET, or when the SSP module is disabled. The STOP (P) and START (S) bits will toggle based on the START and STOP conditions. Control of the I 2C bus may be taken when the P bit is set, or the bus is IDLE and both the S and P bits are clear.
PIC16F818/819 NOTES: DS39598C-page 80 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 11.0 ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The A/D module has four registers: The Analog-to-Digital (A/D) converter module has five inputs for 18/20 pin devices. The conversion of an analog input signal results in a corresponding 10-bit digital number. The A/D module has high and low voltage reference input that is software selectable to some combination of VDD, VSS, RA2, or RA3. The A/D converter has a unique feature of being able to operate while the device is in SLEEP mode.
PIC16F818/819 REGISTER 11-2: ADCON1: A/D CONTROL REGISTER 1 (ADDRESS 9Fh) R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 ADFM ADCS2 — — PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 bit 7 ADFM: A/D Result Format Select bit 1 = Right justified, 6 Most Significant bits of ADRESH are read as ‘0’ 0 = Left justified, 6 Least Significant bits of ADRESL are read as ‘0’ bit 6 ADCS2: A/D Clock Divide by 2 Select bit 1 = A/D Clock source is divided by 2 when system clock is used 0 = Disabled bit 5-4 Unimpl
PIC16F818/819 The ADRESH:ADRESL registers contain the result of the A/D conversion. When the A/D conversion is complete, the result is loaded into the A/D result register pair, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is shown in Figure 11-1. These steps should be followed for doing an A/D conversion: 1. After the A/D module has been configured as desired, the selected channel must be acquired before the conversion is started.
PIC16F818/819 11.1 A/D Acquisition Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (CHOLD) must be allowed to fully charge to the input channel voltage level. The analog input model is shown in Figure 11-2. The source impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge the capacitor CHOLD. The sampling switch (RSS) impedance varies over the device voltage (VDD), see Figure 11-2.
PIC16F818/819 11.2 Selecting the A/D Conversion Clock 11.3 The A/D conversion time per bit is defined as TAD. The A/D conversion requires 9.0 TAD per 8-bit conversion. The source of the A/D conversion clock is software selectable. The seven possible options for TAD are: • • • • • • • The ADCON1, and TRISA registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their corresponding TRIS bits set (input).
PIC16F818/819 11.4 A/D Conversions 11.4.1 A/D RESULT REGISTERS The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select bit (ADFM) controls this justification. Figure 11-4 shows the operation of the A/D result justification. The extra bits are loaded with ‘0’s.
PIC16F818/819 11.5 A/D Operation During SLEEP 11.6 The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction cycle before starting the conversion. This allows the SLEEP instruction to be executed, which eliminates all digital switching noise from the conversion.
PIC16F818/819 NOTES: DS39598C-page 88 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 12.
PIC16F818/819 REGISTER 12-1: R/P-1 CP R/P-1 CONFIGURATION WORD (ADDRESS 2007h)(1) R/P-1 R/P-1 R/P-1 R/P-1 CCPMX DEBUG WRT1 R/P-1 WRT0 CPD LVP R/P-1 R/P-1 R/P-1 R/P-1 BOREN MCLRE FOSC2 PWRTEN R/P-1 R/P-1 R/P-1 WDTEN F0SC1 F0SC0 bit13 bit0 bit 13 CP: Flash Program Memory Code Protection bit 1 = Code protection off 0 = All memory locations code protected bit 12 CCPMX: CCP1 Pin Selection bit 1 = CCP1 function on RB2 0 = CCP1 function on RB3 bit 11 DEBUG: In-Circuit Debugger Mode bit
PIC16F818/819 12.2 RESET The PIC16F818/819 differentiates between various kinds of RESET: • • • • • • Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset during normal operation WDT Wake-up during SLEEP Brown-out Reset (BOR) Some registers are not affected in any RESET condition. Their status is unknown on POR and unchanged in any other RESET.
PIC16F818/819 12.3 MCLR 12.5 PIC16F818/819 device has a noise filter in the MCLR Reset path. The filter will detect and ignore small pulses. It should be noted that a WDT Reset does not drive MCLR pin low. The behavior of the ESD protection on the MCLR pin has been altered from previous devices of this family. Voltages applied to the pin that exceed its specification can result in both MCLR and excessive current beyond the device specification during the ESD event.
PIC16F818/819 12.9 Power Control/Status Register (PCON) if bit BOR cleared, indicating a Brown-out Reset occurred. When the Brown-out Reset is disabled, the state of the BOR bit is unpredictable. The Power Control/Status Register, PCON, has two bits to indicate the type of RESET that last occurred. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The user must set this bit following a Power-on Reset. Bit0 is Brown-out Reset Status bit, BOR.
PIC16F818/819 TABLE 12-4: Register W INDF TMR0 PCL STATUS FSR PORTA PORTB PCLATH INTCON INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset xxxx xxxx N/A xxxx xxxx 0000h 0001 xxxx xxx0 xxxx ---0 0000 1xxx xxxx 0000 xxxx 0000 000x MCLR Reset, WDT Reset uuuu uuuu N/A uuuu uuuu 0000h 000q uuuu uuu0 uuuu ---0 0000 quuu(3) uuuu 0000 uuuu 0000 000u Wake-up via WDT or Interrupt uuuu uuuu N/A uuuu uuuu PC + 1(2) uuuq uuuu uuuu uuuu ---u uuuu quuu(3) uuuu uuuu uuuu uuuu uuuu(1) PIR1 -0
PIC16F818/819 FIGURE 12-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH PULL-UP RESISTOR) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 12-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD THROUGH RC NETWORK): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT IN
PIC16F818/819 FIGURE 12-6: SLOW RISE TIME (MCLR TIED TO VDD THROUGH RC NETWORK) 5V 1V 0V VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET 12.10 Interrupts The PIC16F818/819 has up to nine sources of interrupt. The interrupt control register (INTCON) records individual interrupt requests in flag bits. It also has individual and global interrupt enable bits. Note: Individual interrupt flag bits are set, regardless of the status of their corresponding mask bit or the GIE bit.
PIC16F818/819 12.10.1 INT INTERRUPT 12.10.3 External interrupt on the RB0/INT pin is edge triggered, either rising, if bit INTEDG (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a valid edge appears on the RB0/INT pin, flag bit INTF (INTCON<1>) is set. This interrupt can be disabled by clearing enable bit INTE (INTCON<4>). Flag bit INTF must be cleared in software in the Interrupt Service Routine before re-enabling this interrupt.
PIC16F818/819 12.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Electrical Specifications section under parameter #31. Values for the WDT prescaler (actually a postscaler, but shared with the Timer0 prescaler) may be assigned using the OPTION register. For PIC16F818/819 devices, the WDT is driven by the INTRC oscillator. When the WDT is enabled, the INTRC (31.25 kHz) oscillator is enabled. The nominal WDT period is 16 ms, and has the same accuracy as the INTRC oscillator.
PIC16F818/819 12.13 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator driver is turned off. The I/O ports maintain the status they had before the SLEEP instruction was executed (driving high, low, or hi-impedance).
PIC16F818/819 FIGURE 12-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 TOST(2) CLKO(4) INT pin INTF Flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in SLEEP INSTRUCTION FLOW PC Instruction Fetched Instruction Executed Note 1: 2: 3: 4: PC PC+1 Inst(PC) = SLEEP Inst(PC - 1) PC+2 PC+2 Inst(PC + 1) Inst(PC + 2) SLEEP Inst(PC + 1) PC + 2 Dummy Cycle 0004h 0005h Inst(0004h) Inst(0005h) Dumm
PIC16F818/819 12.17 In-Circuit Serial Programming 12.18 Low Voltage ICSP Programming PIC16F818/819 microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock and data and three other lines for power, ground, and the programming voltage (see Figure 12-10 for an example). This allows customers to manufacture boards with unprogrammed devices, and then program the microcontroller just before shipping the product.
PIC16F818/819 NOTES: DS39598C-page 102 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 13.0 INSTRUCTION SET SUMMARY The PIC16 instruction set is highly orthogonal and is comprised of three basic categories: • Byte-oriented operations • Bit-oriented operations For example, a “clrf PORTB” instruction will read PORTB, clear all the data bits, then write the result back to PORTB. This example would have the unintended result that the condition that sets the RBIF flag would be cleared.
PIC16F818/819 TABLE 13-2: PIC16F818/819 INSTRUCTION SET Mnemonic, Operands Description Cycles 14-Bit Opcode MSb LSb Status Affected Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f f, d f, d f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f
PIC16F818/819 13.2 Instruction Descriptions ADDLW Add Literal and W ANDWF AND W with f Syntax: [ label ] ADDLW Syntax: [ label ] ANDWF Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operation: (W) + k → (W) Status Affected: C, DC, Z Operation: (W) .AND. (f) → (destination) The contents of the W register are added to the eight-bit literal ‘k’ and the result is placed in the W register. Status Affected: Z Description: AND the W register with register ‘f’.
PIC16F818/819 BTFSS Bit Test f, Skip if Set CLRF Clear f Syntax: [ label ] BTFSS f,b Syntax: [ label ] CLRF Operands: 0 ≤ f ≤ 127 0≤b<7 Operands: 0 ≤ f ≤ 127 Operation: Operation: skip if (f) = 1 00h → (f) 1→Z Status Affected: None Status Affected: Z Description: If bit ‘b’ in register ‘f’ = ‘0’, the next instruction is executed. If bit ‘b’ = ‘1’, then the next instruction is discarded and a NOP is executed instead, making this a 2 TCY instruction.
PIC16F818/819 COMF Complement f Syntax: [ label ] COMF GOTO Unconditional Branch Syntax: [ label ] Operands: 0 ≤ f ≤ 127 d ∈ [0,1] Operands: 0 ≤ k ≤ 2047 Operation: (f) → (destination) Operation: k → PC<10:0> PCLATH<4:3> → PC<12:11> Status Affected: Z Status Affected: None Description: The contents of register ‘f’ are complemented. If ‘d’ = ‘0’, the result is stored in W. If ‘d’ = ‘1’, the result is stored back in register ‘f’. Description: GOTO is an unconditional branch.
PIC16F818/819 IORLW Inclusive OR Literal with W MOVLW Move Literal to W Syntax: [ label ] Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: (W) .OR. k → (W) Operation: k → (W) Status Affected: Z Status Affected: None Description: The contents of the W register are OR’d with the eight-bit literal ‘k’. The result is placed in the W register. Description: The eight-bit literal ‘k’ is loaded into W register. The don’t cares will assemble as ‘0’s.
PIC16F818/819 RETFIE Return from Interrupt RLF Rotate Left f through Carry Syntax: [ label ] Syntax: [ label ] Operands: None Operands: Operation: TOS → PC, 1 → GIE 0 ≤ f ≤ 127 d ∈ [0,1] Operation: See description below Status Affected: None Status Affected: C Description: The contents of register ‘f’ are rotated one bit to the left through the Carry Flag. If ‘d’ = ‘0’, the result is placed in the W register. If ‘d’ = ‘1’, the result is stored back in register ‘f’.
PIC16F818/819 SUBLW Syntax: Subtract W from Literal [ label ] SUBLW k XORLW Exclusive OR Literal with W Syntax: [ label ] Operands: 0 ≤ k ≤ 255 Operands: 0 ≤ k ≤ 255 Operation: k - (W) → (W) XORLW k Operation: (W) .XOR. k → (W) Status Affected: C, DC, Z Status Affected: Z Description: The W register is subtracted (2’s complement method) from the eight-bit literal ‘k’. The result is placed in the W register.
PIC16F818/819 14.
PIC16F818/819 14.4 MPLINK Object Linker/ MPLIB Object Librarian 14.6 The MPLINK object linker combines relocatable objects created by the MPASM assembler and the MPLAB C17 and MPLAB C18 C compilers. It can also link relocatable objects from pre-compiled libraries, using directives from a linker script. The MPLIB object librarian is a librarian for precompiled code to be used with the MPLINK object linker.
PIC16F818/819 14.8 MPLAB ICD In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD, is a powerful, low cost, run-time development tool. This tool is based on the FLASH PICmicro MCUs and can be used to develop for this and other PICmicro microcontrollers. The MPLAB ICD utilizes the in-circuit debugging capability built into the FLASH devices.
PIC16F818/819 14.13 PICDEM 3 Low Cost PIC16CXXX Demonstration Board The PICDEM 3 demonstration board is a simple demonstration board that supports the PIC16C923 and PIC16C924 in the PLCC package. It will also support future 44-pin PLCC microcontrollers with an LCD Module. All the necessary hardware and software is included to run the basic demonstration programs.
Software Tools Programmers Debugger Emulators PIC12CXXX PIC14000 PIC16C5X PIC16C6X PIC16CXXX PIC16F62X PIC16C7X 9 9 9 9 9 9 2002 Microchip Technology Inc. Preliminary 9 9 9 † † 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 MCP2510 * Contact the Microchip Technology Inc. web site at www.microchip.
PIC16F818/819 NOTES: DS39598C-page 116 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 15.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................ -55°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on any pin with respect to VSS (except VDD and MCLR) ................................................... -0.
PIC16F818/819 FIGURE 15-1: PIC16F818/819 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 16 MHz 20 MHz Frequency FIGURE 15-2: PIC16LF818/819 VOLTAGE-FREQUENCY GRAPH 6.0V 5.5V Voltage 5.0V 4.5V 4.0V 3.5V 3.0V 2.5V 2.0V 4 MHz 10 MHz Frequency FMAX = (12 MHz/V) (VDDAPPMIN - 2.5V) + 4 MHz Note 1: VDDAPPMIN is the minimum voltage of the PICmicro® device in the application. Note 2: FMAX has a maximum frequency of 10 MHz.
PIC16F818/819 15.1 DC Characteristics: Supply Voltage PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No. Device Typ Max Units Conditions 0.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.2 DC Characteristics: Power-down and Supply Current PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) PIC16LF818/819 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.3 DC Characteristics: Internal RC Accuracy PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) PIC16F818 (Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial PIC16F818/819 (Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Param No.
PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) DC CHARACTERISTICS Param No. Sym VIL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 15.1.
PIC16F818/819 15.4 DC Characteristics: PIC16F818/819 (Industrial, Extended) PIC16LF818/819 (Industrial) (Continued) DC CHARACTERISTICS Param No. Sym VOL Characteristic Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial -40°C ≤ TA ≤ +125°C for extended Operating voltage VDD range as described in DC Specification, Section 15.1. Min Typ† Max Units Conditions Output Low Voltage D080 I/O ports — — 0.6 V IOL = 8.5 mA, VDD = 4.
PIC16F818/819 15.5 Timing Parameter Symbology The timing parameter symbols have been created using one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4.
PIC16F818/819 FIGURE 15-4: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 OSC1 1 3 4 3 4 2 CLKO TABLE 15-1: Parameter No. EXTERNAL CLOCK TIMING REQUIREMENTS Sym FOSC Characteristic External CLKI Frequency (Note 1) Oscillator Frequency (Note 1) 1 TOSC Min Typ† Max Units DC — 4 MHz XT and RC Osc mode DC — 20 MHz HS Osc mode DC — 200 DC — 4 kHz Conditions LP Osc mode MHz RC Osc mode 0.
PIC16F818/819 FIGURE 15-5: CLKO AND I/O TIMING Q1 Q4 Q2 Q3 OSC1 11 10 CLKO 13 19 14 12 18 16 I/O Pin (Input) 15 17 I/O Pin (Output) New Value Old Value 20, 21 Note: Refer to Figure 15-3 for load conditions. TABLE 15-2: Param No.
PIC16F818/819 FIGURE 15-6: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR 30 Internal POR 33 PWRT Time-out 32 OSC Time-out Internal RESET Watchdog Timer Reset 31 34 34 I/O Pins Note: Refer to Figure 15-3 for load conditions. FIGURE 15-7: BROWN-OUT RESET TIMING VBOR VDD 35 TABLE 15-3: Parameter No.
PIC16F818/819 FIGURE 15-8: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS RA4/T0CKI 41 40 42 RB6/T1OSO/T1CKI 46 45 47 48 TMR0 or TMR1 Note: Refer to Figure 15-3 for load conditions. TABLE 15-4: Param No. 40* 41* 42* 45* 46* 47* TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS Symbol Tt0H Tt0L Tt0P Tt1H Tt1L Tt1P Characteristic T0CKI High Pulse Width T0CKI Low Pulse Width T0CKI Period 48 Typ† Max Units Conditions No Prescaler 0.
PIC16F818/819 FIGURE 15-9: CAPTURE/COMPARE/PWM TIMINGS (CCP1) CCP1 (Capture Mode) 50 51 52 CCP1 (Compare or PWM Mode) 53 54 Note: Refer to Figure 15-3 for load conditions. TABLE 15-5: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1) Param Symbol No. 50* TccL Characteristic CCP1 No Prescaler Input Low Time Min PIC16F818/819 With Prescaler PIC16LF818/819 51* TccH CCP1 Input High Time No Prescaler PIC16F818/819 With Prescaler PIC16LF818/819 Typ† Max Units 0.
PIC16F818/819 FIGURE 15-10: SPI MASTER MODE TIMING (CKE = 0, SMP = 0) SS 70 SCK (CKP = 0) 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit6 - - - - - -1 MSb SDO LSb 75, 76 SDI Bit6 - - - -1 MSb In LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-11: SPI MASTER MODE TIMING (CKE = 1, SMP = 1) SS 81 SCK (CKP = 0) 71 72 79 73 SCK (CKP = 1) 80 78 SDO MSb Bit6 - - - - - -1 LSb Bit6 - - - -1 LSb In 75, 76 SDI MSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F818/819 FIGURE 15-12: SPI SLAVE MODE TIMING (CKE = 0) SS 70 SCK (CKP = 0) 83 71 72 78 79 79 78 SCK (CKP = 1) 80 Bit6 - - - - - -1 MSb SDO LSb 77 75, 76 SDI MSb In Bit6 - - - -1 LSb In 74 73 Note: Refer to Figure 15-3 for load conditions. FIGURE 15-13: SPI SLAVE MODE TIMING (CKE = 1) 82 SS SCK (CKP = 0) 70 83 71 72 SCK (CKP = 1) 80 SDO MSb Bit6 - - - - - -1 LSb 75, 76 SDI MSb In 77 Bit6 - - - -1 LSb In 74 Note: Refer to Figure 15-3 for load conditions.
PIC16F818/819 TABLE 15-6: Param No.
PIC16F818/819 TABLE 15-7: Param No.
PIC16F818/819 TABLE 15-8: Param. No. 100* I2C BUS DATA REQUIREMENTS Symbol THIGH Characteristic Clock high time 100 kHz mode 400 kHz mode TLOW Clock low time 103* 90* 91* 106* 107* 92* 109* 110* TR TF TSU:STA THD:STA THD:DAT TSU:DAT TSU:STO TAA TBUF CB Units 4.0 — µs µs 0.6 — — 100 kHz mode 4.7 — µs 400 kHz mode 1.3 — µs SSP Module 102* Max 1.5 TCY SSP Module 101* Min Conditions 1.5 TCY — SDA and SCL rise time 100 kHz mode — 1000 ns 400 kHz mode 20 + 0.
PIC16F818/819 TABLE 15-9: A/D CONVERTER CHARACTERISTICS: PIC16F818/819 (INDUSTRIAL, EXTENDED) PIC16LF818/819 (INDUSTRIAL) Param Sym No. Characteristic Min Typ† Max Units Conditions A01 NR Resolution — — 10 bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential linearity error — — <±1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A06 EOFF Offset error — — <±2 LSb VREF = VDD = 5.
PIC16F818/819 FIGURE 15-16: A/D CONVERSION TIMING BSF ADCON0, GO 1 TCY (TOSC/2)(1) 131 Q4 130 A/D CLK 132 9 A/D DATA 8 ... 7 ... 2 1 NEW_DATA OLD_DATA ADRES 0 ADIF GO DONE SAMPLING STOPPED SAMPLE Note 1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. TABLE 15-10: A/D CONVERSION REQUIREMENTS Param No. 130 Sym TAD Characteristic A/D clock period Min Typ† Max Units PIC16F818/819 1.
PIC16F818/819 NOTES: DS39598C-page 142 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 16.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES No Graphs and Tables are available at this time. 2002 Microchip Technology Inc.
PIC16F818/819 NOTES: DS39598C-page 144 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 17.0 PACKAGING INFORMATION 17.1 Package Marking Information 18-Lead PDIP Example XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN PIC16F818-I/P 0210017 18-Lead SOIC Example XXXXXXXXXXXX XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC16F818-04 /SO 0210017 20-Lead SSOP Example XXXXXXXXXXX XXXXXXXXXXX YYWWNNN PIC16F81820/SS 0210017 Example 28-Lead QFN PIC16F81 8-I/ML 0210017 XXXXXXXX XXXXXXXX YYWWNNN Legend: Note: * XX...
PIC16F818/819 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n α 1 E A2 A L c A1 B1 β p B eB Units Dimension Limits n p MIN INCHES* NOM 18 .100 .155 .130 MAX MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN Number of Pins Pitch Top to Seating Plane A .140 .170 Molded Package Thickness A2 .115 .145 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .
PIC16F818/819 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h α 45° c A2 A φ β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 A1 INCHES* NOM 18 .050 .099 .
PIC16F818/819 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B 2 1 n α c A2 A φ L A1 β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .
PIC16F818/819 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) EXPOSED METAL PADS E E1 Q D1 D D2 p 2 1 B n R E2 CH x 45 TOP VIEW L BOTTOM VIEW α A2 A A1 A3 Units Dimension Limits Number of Pins INCHES MIN MILLIMETERS* NOM n MIN MAX MAX NOM 28 28 Pitch p Overall Height A .033 .039 0.85 1.00 Molded Package Thickness A2 .026 .031 0.65 0.80 Standoff A1 .0004 .002 0.01 0.05 Base Thickness A3 .008 REF. 0.20 REF. 6.00 BSC .026 BSC .000 E .
PIC16F818/819 28-Lead Plastic Quad Flat No Lead Package (ML) 6x6 mm Body (QFN) Land Pattern and Solder Mask M B L M p PACKAGE EDGE SOLDER MASK Pitch Pad Width Pad Length Pad to Solder Mask Units Dimension Limits p B L M MIN .009 .020 .005 INCHES NOM .026 BSC .011 .024 MAX .014 .030 .006 MILLIMETERS* NOM 0.65 BSC 0.23 0.28 0.50 0.60 0.13 MIN MAX 0.35 0.75 0.15 *Controlling Parameter Drawing No. C04-2114 DS39598C-page 150 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 APPENDIX A: REVISION HISTORY Version Date A May 2002 B August 2002 C Revision Description This is a new data sheet. Added INTRC section. PWRT and BOR are independent of each other. Revised program memory text and code routine. Added QFN package. Modified PORTB diagrams. November 2002 Added various new feature descriptions. Added Internal RC Oscillator specifications. Added Low Power Timer1 specifications and RTC application example.
PIC16F818/819 NOTES: DS39598C-page 152 Preliminary 2002 Microchip Technology Inc.
PIC16F818/819 INDEX A A/D Acquisition Requirements .......................................... 84 ADIF Bit ...................................................................... 83 Analog-to-Digital Converter ........................................ 81 Associated Registers ................................................. 87 Calculating Acquisition Time ...................................... 84 Configuring Analog Port Pins ..................................... 85 Configuring the Interrupt ...................
PIC16F818/819 I2C D Data EEPROM Memory ..................................................... 25 Associated Registers ................................................. 32 EEADR Register ........................................................ 25 EEADRH Register ...................................................... 25 EECON1 Register ...................................................... 25 EECON2 Register ...................................................... 25 EEDATA Register ............................
PIC16F818/819 INTCON Register ............................................................... 15 GIE Bit ........................................................................ 18 INTE Bit ...................................................................... 18 INTF Bit ...................................................................... 18 RBIF Bit ...................................................................... 18 TMR0IE Bit .................................................................
PIC16F818/819 Power-on Reset (POR) ...............................89, 91, 92, 93, 94 POR Status (POR Bit) ................................................ 22 Power Control (PCON) Register ................................ 93 Power-down (PD Bit) .................................................. 91 Time-out (TO Bit) ................................................. 16, 91 Power-up Timer (PWRT) .............................................. 89, 92 PR2 Register ..................................................
PIC16F818/819 T T1CKPS0 Bit ...................................................................... 57 T1CKPS1 Bit ...................................................................... 57 T1OSCEN Bit ..................................................................... 57 T1SYNC Bit ........................................................................ 57 T2CKPS0 Bit ...................................................................... 64 T2CKPS1 Bit ......................................................
PIC16F818/819 NOTES: DS39598C-page 158 Preliminary 2002 Microchip Technology Inc.
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PIC16F818/819 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document.
PIC16F818/819 PIC16F818/819 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX XXX Package Pattern Examples: a) b) Device PIC16F818: Standard VDD range PIC16F818T: (Tape and Reel) PIC16LF818: Extended VDD range Temperature Range I Package P SO SS ML = = PIC16F818-I/P = Industrial temp., PDIP package, Extended VDD limits. PIC16F818-I/SO = Industrial temp.
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