Datasheet

PIC16F631/677/685/687/689/690
DS40001262F-page 34 2005-2015 Microchip Technology Inc.
TABLE 2-4: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 3
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 3
180h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
181h OPTION_REG RABPU
INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111
36,200
182h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
183h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 35,200
184h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
185h TRISA
TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 --11 1111 57,200
186h TRISB TRISB7 TRISB6 TRISB5 TRISB4
1111 ---- 68,201
187h TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0 1111 1111 74,201
188h Unimplemented
189h Unimplemented
18Ah PCLATH
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
18Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
(1)
0000 000x
37,200
18Ch EECON1 EEPGD
(2)
WRERR WREN WR RD x--- x000 119,201
18Dh EECON2 EEPROM Control Register 2 (not a physical register) ---- ---- 117,201
18Eh Unimplemented
18Fh Unimplemented
190h Unimplemented
191h Unimplemented
192h Unimplemented
193h Unimplemented
194h Unimplemented
195h Unimplemented
196h Unimplemented
197h Unimplemented
198h Unimplemented
199h Unimplemented
19Ah Unimplemented
19Bh Unimplemented
19Ch Unimplemented
19Dh PSTRCON
(2)
STRSYNC STRD STRC STRB STRA ---0 0001 144,201
19Eh SRCON SR1 SR0 C1SEN C2REN PULSS PULSR
0000 00-- 101,201
19Fh Unimplemented
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F690 only.