Datasheet

2005-2015 Microchip Technology Inc. DS40001262F-page 33
PIC16F631/677/685/687/689/690
TABLE 2-3: PIC16F631/677/685/687/689/690 SPECIAL FUNCTION REGISTERS SUMMARY BANK 2
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Value on
POR, BOR
Page
Bank 2
100h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 43,200
101h TMR0 Timer0 Module Register xxxx xxxx 79,200
102h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 43,200
103h STATUS IRP RP1 RP0 TO
PD ZDCC0001 1xxx 35,200
104h FSR Indirect Data Memory Address Pointer xxxx xxxx 43,200
105h PORTA
(4)
RA5 RA4 RA3 RA2 RA1 RA0 --xx xxxx 57,200
106h PORTB
(4)
RB7 RB6 RB5 RB4 xxxx ---- 67,200
107h PORTC
(4)
RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx 74,200
108h Unimplemented
109h Unimplemented
10Ah PCLATH
Write Buffer for the upper 5 bits of the Program Counter ---0 0000 43,200
10Bh INTCON GIE PEIE T0IE INTE RABIE T0IF INTF RABIF
(1)
0000 000x 37,200
10Ch
EEDAT EEDAT7 EEDAT6 EEDAT5 EEDAT4 EEDAT3 EEDAT2 EEDAT1 EEDAT0 0000 0000 118,201
10Dh
EEADR EEADR7
(3)
EEADR6 EEADR5 EEADR4 EEADR3 EEADR2 EEADR1 EEADR0 0000 0000 118,201
10Eh EEDATH
(2)
EEDATH5 EEDATH4 EEDATH3 EEDATH2 EEDATH1 EEDATH0
--00 0000 118,201
10Fh EEADRH
(2)
EEADRH3 EEADRH2 EEADRH1 EEADRH0
---- 0000 118,201
110h Unimplemented
111h Unimplemented
112h Unimplemented
113h Unimplemented
114h Unimplemented
115h WPUB WPUB7 WPUB6 WPUB5 WPUB4
1111 ---- 68,201
116h IOCB IOCB7 IOCB6 IOCB5 IOCB4
0000 ---- 68,201
117h Unimplemented
118h VRCON C1VREN C2VREN VRR VP6EN VR3 VR2 VR1 VR0 0000 0000 103,201
119h CM1CON0 C1ON C1OUT
C1OE C1POL C1R C1CH1 C1CH0 0000 -000 96,201
11Ah CM2CON0 C2ON C2OUT
C2OE C2POL C2R C2CH1 C2CH0 0000 -000 97,201
11Bh CM2CON1 MC1OUT MC2OUT
T1GSS C2SYNC 00-- --10 99,201
11Ch Unimplemented
11Dh Unimplemented
11Eh ANSEL ANS7 ANS6 ANS5 ANS4 ANS3
(3)
ANS2
(3)
ANS1 ANS0 1111 1111 59,201
11Fh ANSELH
(3)
ANS11 ANS10 ANS9 ANS8 ---- 1111 113,201
Legend: – = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition, shaded = unimplemented
Note 1: MCLR
and WDT Reset does not affect the previous value data latch. The RABIF bit will be cleared upon Reset but will set again if the
mismatch exists.
2: PIC16F685/PIC16F689/PIC16F690 only.
3: PIC16F677/PIC16F685/PIC16F687/PIC16F689/PIC16F690 only.
4: Port pins with analog functions controlled by the ANSEL and ANSELH registers will read ‘0’ immediately after a Reset even though the
data latches are either undefined (POR) or unchanged (other Resets).