Datasheet

PIC16F631/677/685/687/689/690
DS40001262F-page 192  2005-2015 Microchip Technology Inc.
FIGURE 13-12: CLOCK SYNCHRONIZATION TIMING
TABLE 13-4: REGISTERS ASSOCIATED WITH I
2
C™ OPERATION
(1)
Addr Name Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0
Value on
POR, BOR
Value on
all other
Resets
0Bh/8Bh/
10Bh/18Bh
INTCON GIE PEIE
T0IE INTE RABIE T0IF INTF RABIF 0000 000x 0000 000x
0Ch PIR1
— ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF -000 0000 -000 0000
13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu
14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000
86h TRISB TRISB7 TRISB6 TRISB5 TRISB4
— — — — 1111 ---- 1111 ----
93h SSPMSK
(2)
MSK7 MSK6 MSK5 MSK4 MSK3 MSK2 MSK1 MSK0 1111 1111 1111 1111
94h SSPSTAT SMP
(3)
CKE
(3)
D/A PSR/WUA BF 0000 0000 0000 0000
8Ch PIE1
— ADIE RCIE TXIE SSPIE CCP1IE TMR2IF TMR1IF -000 0000 -000 0000
Legend: – = Unimplemented locations, read as ‘0’, u = unchanged, x = unknown. Shaded cells are not used by the SSP module.
Note 1: PIC16F677/PIC16F687/PIC16F689/PIC16F690 only.
2: SSPMSK register (Register 13-3) can be accessed by reading or writing to SSPADD register with bits SSPM<3:0> = 1001.
See Registers 13-2 and 13-3 for more details.
3: Maintain these bits clear.
SDA
SCL
DX-1DX
WR
Table 0-1:
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
Q
1
Q
2
Q
3
Q
4
SSPCON
CKP
Master device
deasserts clock
Master device
asserts clock