Datasheet

2010 Microchip Technology Inc. DS40039F-page 11
PIC16F630/676
TABLE 2-1: PIC16F630/676 SPECIAL REGISTERS SUMMARY BANK 0
AddrNameBit 7Bit 6Bit 5Bit 4Bit 3Bit 2 Bit 1Bit 0
Value on
POR,
BOD
Page
Bank 0
00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) xxxx xxxx 20,63
01h TMR0 Timer0 Module’s Register xxxx xxxx 31
02h PCL Program Counter’s (PC) Least Significant Byte 0000 0000 19
03h STATUS
IRP
(2)
RP1
(2)
RP0 TO PD ZDCC
0001 1xxx 13
04h FSR Indirect data memory Address Pointer xxxx xxxx 20
05h PORTA
I/O Control Registers --xx xxxx 21
06h Unimplemented
07h PORTC
I/O Control Registers --xx xxxx 28
08h Unimplemented
09h Unimplemented
0Ah PCLATH
Write buffer for upper 5 bits of program counter ---0 0000 19
0Bh INTCON GIE PEIE T0IE INTE RAIE T0IF INTF RAIF 0000 0000 15
0Ch PIR1
EEIF ADIF —CMIF —TMR1IF00-- 0--0 17
0Dh Unimplemented
0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 xxxx xxxx 34
0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 xxxx xxxx 34
10h T1CON
T1GE T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON
-000 0000 36
11h Unimplemented
12h Unimplemented
13h Unimplemented
14h Unimplemented
15h Unimplemented
16h Unimplemented
17h Unimplemented
18h Unimplemented
19h CMCON
—COUT CINV CIS CM2 CM1 CM0 -0-0 0000 39
1Ah Unimplemented
1Bh Unimplemented
1Ch Unimplemented
1Dh Unimplemented
1Eh ADRESH
(3)
Most Significant 8 bits of the left shifted A/D result or 2 bits of right shifted result xxxx xxxx 46
1Fh ADCON0
(3)
ADFM VCFG CHS2 CHS1 CHS0 GO/DONE ADON
00-0 0000 47,63
Legend: = Unimplemented locations read as ‘0’, u = unchanged, x = unknown, q = value depends on condition shaded = unimplemented
Note 1: Other (non Power-up) Resets include MCLR
Reset, Brown-out Detect and Watchdog Timer Reset during normal operation.
2: IRP and RP1 bits are reserved, always maintain these bits clear.
3: PIC16F676 only.