Datasheet

 2011-2017 Microchip Technology Inc. DS40001574D-page 199
PIC16(L)F1938/9
23.2.5 COMPARE DURING SLEEP
The Compare mode is dependent upon the system
clock (F
OSC) for proper operation. Since FOSC is shut
down during Sleep mode, the Compare mode will not
function properly during Sleep.
23.2.6 ALTERNATE PIN LOCATIONS
This module incorporates I/O pins that can be moved to
other locations with the use of the alternate pin function
register, APFCON. To determine which pins can be
moved and what their default locations are upon a
Reset, see
Section 12.1 “Alternate Pin Function” for
more information.
TABLE 23-4: SUMMARY OF REGISTERS ASSOCIATED WITH COMPARE
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
APFCON
— CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL 118
CCPxCON
PxM<1:0>
(1)
DCxB<1:0> CCPxM<3:0>
218
CCPRxL Capture/Compare/PWM Register x Low Byte (LSB)
196
CCPRxH Capture/Compare/PWM Register x High Byte (MSB)
196
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
87
PIE1 TMR1GIE ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE
88
PIE2 OSFIE C2IE C1IE EEIE BCLIE LCDIE — CCP2IE
89
PIE3
— CCP5IE CCP4IE CCP3IE TMR6IE — TMR4IE —
90
PIR1 TMR1GIF
ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF
91
PIR2
OSFIF C2IF C1IF EEIF BCLIF LCDIF —CCP2IF
92
PIR3 — CCP5IF CCP4IF CCP3IF TMR6IF — TMR4IF —
93
T1CON TMR1CS<1:0> T1CKPS<1:0> T1OSCEN T1SYNC
—TMR1ON
188
T1GCON TMR1GE T1GPOL T1GTM T1GSPM T1GGO/DONE T1GVAL T1GSS<1:0>
189
TMR1L Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
184
TMR1H Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
184
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
120
TRISB TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0
125
TRISC TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
129
TRISD
(2)
TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0
132
TRISE
— — — — —
(3)
TRISE2
(2)
TRISE1
(2)
TRISE0
(2)
135
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by Compare mode.
Note 1: Applies to ECCP modules only.
2: These bits are not implemented on PIC16(L)F1938 devices, read as ‘0’.
3: Unimplemented, read as ‘1’.