Datasheet
2009 Microchip Technology Inc. Preliminary DS41364D-page 247
PIC16F193X/LF193X
23.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if enabled, will wake the
device.
TABLE 23-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register
on Page
ANSELA
— — ANSA5 ANSA4 ANSA3 ANSA2 ANSA1 ANSA0
133
APFCON
— CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL CCP2SEL
130
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF
99
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE
100
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
103
SSPBUF
Synchronous Serial Port Receive Buffer/Transmit Register
241*
SSPCON1 WCOL SSPOV SSPEN CKP SSPM<3:0>
285
SSPCON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN
287
SSPSTAT SMP CKE
D/A P S R/W UA BF 284
TRISA
TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
132
TRISC
TRISC7 TRISC6 TRISC5 TRISC4 TRISC3 TRISB2 TRISC1 TRISC0
140
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
* Page provides register information.