Datasheet

 2010-2011 Microchip Technology Inc. Preliminary DS41440B-page 299
PIC16(L)F1825/1829
FIGURE 26-4: ASYNCHRONOUS TRANSMISSION (BACK-TO-BACK)
TABLE 26-1: SUMMARY OF REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
APFCON0 RXDTSEL
SDOSEL
(2)
SSSEL
(2)
— T1GSEL TXCKSEL — —
123
BAUDCON
ABDOVF RCIDL — SCKP BRG16 — WUE ABDEN 306
INLVLA
(3)
— — INLVLA5 INLVLA4 INLVLA3 INLVLA2 INLVLA1 INLVLA0 129
INLVLB
(1)
INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 134
INLVLC
INLVLC7
(1)
INLVLC6
(1)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1 INLVLC0 140
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 93
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF
97
RCSTA SPEN
RX9 SREN CREN ADDEN FERR OERR RX9D 305
SPBRGL BRG<7:0> 307*
SPBRGH BRG<15:8> 307*
TRISA
— — TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0
127
TRISB
(1)
TRISB7 TRISB6 TRISB5 TRISB4 — — — —
133
TRISC
TRISC7
(1)
TRISC6
(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1 TRISC0
138
TXREG
EUSART Transmit Data Register 297
TXSTA CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 304
Legend: — = unimplemented location, read as ‘0’. Shaded cells are not used for Asynchronous Transmission.
* Page provides register information.
Note 1: PIC16(L)F1829 only.
2: PIC16(L)F1825 only.
3: Unshaded cells apply to PIC16(L)F1825 only.
Transmit Shift Reg.
Write to TXREG
BRG Output
(Shift Clock)
TX/CK
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Word 1
Word 2
Word 1
Word 2
Start bit
Stop bit
Start bit
Transmit Shift Reg.
Word 1
Word 2
bit 0 bit 1
bit 7/8 bit 0
Note: This timing diagram shows two consecutive transmissions.
1 TCY
1 TCY
pin
TXIF bit
(Transmit Buffer
Reg. Empty Flag)