Datasheet

 2010-2011 Microchip Technology Inc. Preliminary DS41440B-page 251
PIC16(L)F1825/1829
25.2.6 SPI OPERATION IN SLEEP MODE
In SPI Master mode, module clocks may be operating
at a different speed than when in full power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the
MSSPx clock is much faster than the system clock.
In Slave mode, when MSSPx interrupts are enabled,
after the master completes sending data, an MSSPx
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSPx inter-
rupts should be disabled.
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the
MSSPx interrupt flag bit will be set and if enabled, will
wake the device.
TABLE 25-1: SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Register on
Page
ANSELA
— — —ANSA4 — ANSA2 ANSA1 ANSA0 127
ANSELB
(1)
ANSB7 ANSB6
ANSB5 ANSB4
— — — — 134
ANSELC
ANSC7
(1)
ANSC6
(1)
— — ANSC3 ANSC2 ANSC1 ANSC0 139
APFCON0 RXDTSEL SDOSEL
(2)
SSSEL
(2)
— T1GSEL TXCKSEL — — 123
APFCON1
— — SDO2SEL
(1)
SS2SEL
(1)
P1DSEL P1CSEL P2BSEL CCP2SEL 124
INLVLA
— — INLVLA5
(1)
INLVLA4
(1)
INLVLA3 INLVLA2 INLVLA1 INLVLA0 129
INLVLB
(1)
INLVLB7 INLVLB6 INLVLB5 INLVLB4 — — — — 134
INLVLC
INLVLC7
(1)
INLVLC6
(1)
INLVLC5 INLVLC4 INLVLC3 INLVLC2 INLVLC1
(1)
INLVLC0
(1)
140
INTCON GIE PEIE
TMR0IE INTE IOCIE TMR0IF INTF IOCIF 92
PIE1
TMR1GIE ADIE RCIE TXIE SSP1IE CCP1IE TMR2IE TMR1IE 93
PIR1
TMR1GIF ADIF RCIF TXIF SSP1IF CCP1IF TMR2IF TMR1IF 97
SSP1BUF Synchronous Serial Port Receive Buffer/Transmit Register 245*
SSP1CON1 WCOL SSPOV SSPEN CKP SSPM<3:0> 290
SSP1CON3
ACKTIM PCIE SCIE BOEN SDAHT SBCDE AHEN DHEN 292
SSP1STAT SMP CKE
D/A P S R/W UA BF 289
TRISA
— —TRISA5
(1)
TRISA4
(1)
TRISA3 TRISA2 TRISA1 TRISA0 127
TRISB
(1)
TRISB7 TRISB6
TRISB5 TRISB4
— — — — 133
TRISC
TRISC7
(1)
TRISC6
(1)
TRISC5 TRISC4 TRISC3 TRISC2 TRISC1
(1)
TRISC0
(1)
138
Legend: — = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP1 in SPI mode.
* Page provides register information.
Note 1: PIC16(L)F1829 only.
2: PIC16(L)F1825 only.